Semiconductor device

ABSTRACT

A semiconductor device is provided wich includes a first wiring and second wirings in which end portions of the second wirings connected to the first wiring are bent parallel to that forms a predetermined angle with respect to the first direction. The first wiring extends along a first direction and has a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside. The second wirings are situated above the first wiring, connected to the first wiring through a contact hole, and affected by the stresses of the first wiring.

TECHNICAL FIELD

The present invention relates to a semiconductor device and, moreparticularly, to a construction for suppressing deterioration ofperformance and reliability due to thermal stresses that are generatedin its composing material.

BACKGROUND ART

Conventionally, there is a semiconductor device which has a multilayerwiring structure. In such a semiconductor device, lower layer wiringsand upper layer wirings are electrically connected through contact holesthat are formed in an interlayer insulating film.

FIG. 13 is a diagram for explaining a wiring structure of such asemiconductor device. FIG. 13(a) is a plan view, and FIG. 13(b) is across-sectional view along a line XIIIb--XIIIb shown in FIG. 13(a). Inthe figure, reference numeral 250 designates a wiring structure that isformed on a silicon substrate 5. This wiring structure 250 has a lowerlayer wiring (first wiring) 1 that extends along a first direction D1and has a wiring width direction in a second direction D2 perpendicularto the first direction D1, and upper layer wirings (second wirings) 2aand 2b that extend along the first direction D1 and are electricallyconnected to the lower layer wiring 1.

More specifically, the lower layer wiring 1 is formed on the siliconsubstrate 5 via an underlying insulating film 6, and the lower layerwiring 1 is covered with an interlayer insulating film 7. Further, theupper layer wirings (second wirings) 2a and 2b are formed on theinterlayer insulating film 7. An end portion 2a₁ of the upper layerwiring 2a is connected to an end portion 1a of the lower layer wiring 1through a contact hole 7a that is formed in the interlayer insulatingfilm 7. An end portion 2b₁ of the upper layer wiring 2b is connected tothe other end portion 1b of the lower layer wiring 1 through a contacthole 7b that is formed in the interlayer insulating film 7.

As a composing material of the upper layer wirings 2a and 2b, a metallicmaterial of a low melting point, such as aluminum, which is relativelylow-priced is used. As a composing material of the lower layer wiring 1,a metallic material of a high melting point, such as platinum andtungsten, is used, because various high temperature processing isusually performed after formation of the lower layer wiring.

By the way, as the conventional semiconductor devices having multilayerwiring structures described above, there have been developed variouscircuits from relatively small-sized integrated circuits mounting, forexample, an amplifier circuit, an oscillating circuit, a power supplycircuit and the like, to relatively large-sized integrated circuits,such as a microprocessor and a memory device. Especially in recentyears, as a kind of non-volatile memory device, a ferroelectric memorydevice with ferroelectric capacitors as capacitors constituting memorycells has been contrived.

The ferroelectric capacitor consists of a pair of electrodes opposite toeach other, and a dielectric layer comprising a ferroelectric materialand sandwiched between both electrodes, and has the hysteresischaracteristic as a relationship between a voltage applied between theboth electrodes and polarizability of the ferroelectric material. Thatis, the ferroelectric capacitor has a construction in which even whenthe electric field (applied voltage) is zero, a remanence of a polarityin accordance with the hysteresis of voltage application remains in theferroelectric layer. In the ferroelectric memory device non-volatilityof the storage data is realized by representing storage data by theremanence of the ferroelectric capacitor.

FIGS. 14 and 15 are diagrams for explaining a conventional ferroelectricmemory device. FIG. 14 is a plan view illustrating a memory cell arrayin the ferroelectric memory device. FIG. 15(a) is a cross-sectional viewof a part along a line XVa--XVa shown in FIG. 14, FIG. 15(b) is across-sectional view of a part along a line XVb--XVb shown in FIG. 14,and FIG. 15(c) is a cross-sectional view of a part along a line XVc--XVcshown in FIG. 14.

In the figures, reference numeral 200 designates a memory cell arrayconstituting a ferroelectric memory device. On a silicon substrate 201,a plurality of transistor regions 220a are arranged in a first directionD1, and an insulating film 202 for element isolation is formed on aportion of the silicon substrate 201, except the transistor regions220a.

On both sides of the transistor regions 220a in a line along the firstdirection D1, lower electrodes (first electrodes) 211 are formed as cellplate electrodes on the insulating film 202 for element isolation viafirst interlayer insulating films 203. The lower electrode 211 comprisesa metallic material of a high melting point, such as platinum, iridium,tungsten and titanium, and has a stripe-shaped plan configurationextending along the first direction D1. On surfaces of the lowerelectrodes 211, ferroelectric layers 213 are formed.

On the ferroelectric layers 213 on the surfaces of the lower electrodes211, upper electrodes (second electrodes) 212 comprising a metallicmaterial of a high melting point, such as platinum, iridium, tungstenand titanium, are formed corresponding to the respective transistorregions 220a. That is, on the ferroelectric layers 213, the plurality ofupper electrodes 212 are arranged along the first direction D1. A planshape of each upper electrode 212 is a rectangular shape having thefirst direction D1 as a longitudinal direction. In addition, as is knownfrom FIG. 14, the area of each upper electrode 212 is smaller than thatof the lower electrode 211. Here, the lower electrode 211, the upperelectrodes 212, and the ferroelectric layer 213 located between theseelectrodes constitute ferroelectric capacitors 210. The surfaces of theferroelectric layers 213 and the surfaces of the upper electrodes 211are covered with second interlayer insulating films 204.

In this case, in order to reduce variations in the characteristics ofthe ferroelectric capacitors 210, i.e., variations in polarizability ofthe ferroelectric layers, and make changes in the characteristic, i.e.,changes in polarizability with passage of time, less, the distancesbetween the adjacent upper electrodes 212 and the areas of the upperelectrodes 212 on the lower electrode 211 are set, considering thermalstresses generated in the lower electrode 211 and the like.

Between the pair of lower electrodes 211 that sandwich the transistorregions 220a opposing to each other, a pair of word lines (secondwirings) 223a and 223b comprising polysilicon is disposed so as tostraddle over the plurality of transistor regions 220a arranged in aline. A source diffusion region 222 and drain diffusion regions 221 of amemory transistor 220 constituting a memory cell are formed on bothsides of the word lines 223a and 223b in each transistor region 220a.Portions of the word lines 223a and 223b located above each transistorregion 220a constitute gate electrodes of the memory transistor 220, andare located on the substrate surface via gate insulating films 202a. Thesurfaces of the diffusion regions 221 and 222 and the word lines 223aand 223b are covered with the first and second interlayer insulatingfilms 203 and 204. In FIG. 14, these interlayer insulating films are notshown.

The source diffusion region 222 located between the pair of word lines223a and 223b in each transistor region 220a is connected to a bit line233b extending along a second direction D2 perpendicular to the firstdirection D1, through a contact hole 205b formed in the first and secondinterlayer insulating films 203 and 204. The drain diffusion regions 221located outside the opposite word lines 223a and 223b in each transistorregion 220a are electrically connected to the upper electrodes 212 viaconnecting wirings 233a. That is, one end of the connecting wiring 233ais connected to the upper electrode 212 through a contact hole 204aformed in the second interlayer insulating film 204. The other end ofthe connecting wiring 233a is connected to the drain diffusion region221 through a contact hole 205a formed in the first and secondinterlayer insulating films 203 and 204.

Both end portions 211a and 211b of the lower electrode 211 are connectedto upper layer wirings 206a and 206b through contact holes 208a and 208bthat are formed in the interlayer insulating films 203 and 204,respectively. The ferroelectric layer 213 formed on the surface of thelower electrode 211 is removed at portions of the lower electrode 211that are connected to the upper layer wirings 206a and 206b.

The lower electrodes 211 and the ferroelectric layers 213 are formed bysuccessively forming films of a metallic material, such as titanium andplatinum, and a ferroelectric material on the interlayer insulating film203 and patterning the films. The upper electrodes 212 are formed byforming a film of a metallic material, such as titanium and platinum, onthe ferroelectric layer 213 and patterning this film. The bit lines233b, the connecting wirings 233a, and the upper layer wirings 206a and206b are formed by patterning a metallic film, such as aluminum, formedon the interlayer insulating film 204. The word lines 223a and 223b areformed by patterning a polysilicon film that is formed on the gateinsulating films 202a and the insulating film 202 for element isolation.

The first interlayer insulating film 203 comprises an insulatingmaterial, such as NSG (oxide silicon based) and BPSG (boron, phosphinedoped oxide silicon), and the second interlayer insulating film 204comprises, for example, PSG (phosphine doped oxide silicon).

As the ferroelectric material composing the ferroelectric layer 213 ofthe ferroelectric capacitors, KNO₃, PbLa₂ O₃ --ZrO₂ --TiO₂, PbTiO₃--PbZrO₃ or the like has been known. In addition, PCT InternationalPublication WO 93/12542 also discloses a ferroelectric material that hasextremely low fatigueness as compared with PbTiO₃ --PbZrO₃, beingsuitable for a ferroelectric memory device.

Also in such a ferroelectric memory device, the wiring structure 250shown in FIGS. 13(a) and 13(b) is employed in peripheral circuits,except a memory cell array. When the lower layer wiring 1 of the wiringstructure 250 comprises the same composing material as the lowerelectrode 211 of the memory cell array 200 described above, for example,platinum, seeing from the viewpoint of simplification of waferprocesses, as shown in FIG. 13(c), it is more advantageous that aferroelectric material layer 3 which is to be a dielectric layer of theferroelectric capacitor remains on a region of the surface of the lowerlayer wiring 1, except portions connected to the upper layer wirings 2aand 2b.

The operation will be described briefly.

In the ferroelectric memory device with the construction as describedabove, when, for example, the word line 223a is selected andsubsequently, one of the lower electrodes 211 (for example, theuppermost lower electrode shown in FIG. 14) is driven, thereby makingthe voltage level thereof the level corresponding to the logical voltage"H", storage data of the ferroelectric capacitors 210 formed on thislower electrode are read out onto the respective bit lines 233b throughthe connecting wirings 233a and the transistors 220. The storage dataread out onto the respective bit lines 233b are amplified by senseamplifiers (not shown) to be output to the outside of the ferroelectricmemory device. Thereafter, the voltage level of the lower electrode 211is made a level corresponding to the logical voltage "L" to make theword line 223a the unselected state, thereby completing the reading out.

However, in such a device in which the lower layer wiring 1 in themultilayer wiring structure comprises a conductive material having alarger thermal expansion coefficient, such as platinum, as theconventional semiconductor device shown in FIG. 13, the lower layerwiring 1 that is formed by high temperature processing contracts atnormal temperature. Therefore, great tensile force is applied to theupper layer wirings 2a and 2b connected to this wiring. Especially whenthe plan shape of the lower layer wiring 1 is a slender shape, thethermal stresses of the lower layer wiring 1 that are applied to theportions connected to the upper layer wirings 2a and 2b become extremelylarge, so that there may be produced breaking of the connection portionsof the lower layer wiring 1 and the upper layer wirings 2a and 2b, andthe upper layer wirings 2a and 2b may break. As described above, thereis a problem in that the thermal stresses generated in the lower layerwiring 1 become obstacles to high reliability of the semiconductordevice.

Also in the conventional ferroelectric memory device with ferroelectriccapacitors shown in FIGS. 14 and 15, since the lower electrode 211 as acell plate electrode has a stripe-shaped plan, the thermal stresses ofthe lower electrode 211 that are applied to the portions connected tothe upper layer wirings 206a and 206b become extremely large, so thatthere may be produced breaking of the connection portions of the lowerelectrode 211 and the upper layer wirings 206a and 206b, and the upperlayer wirings 206a and 206b may break. Further, in addition to thedeterioration of reliability due to the breaking as described above, thethermal stresses of the lower electrode 211 affect the ferroelectriclayer 213 thereon, thereby causing variations in the characteristics anddeterioration of the characteristics of the ferroelectric capacitors. Asa result, there is another problem in that the performance andreliability of the ferroelectric memory device are deteriorated.

The present invention is directed to solving the above-describedconventional problems, and has an object to provide a semiconductordevice in which the influences by stresses generated in a wiring or anelectrode can be reduced, thereby suppressing breaking at wirings and anelectrode, and variations in characteristics and characteristicdeterioration of ferroelectric capacitors that are disposed on theelectrode.

DISCLOSURE OF THE INVENTION

In order to achieve the object, a semiconductor device of claim 1includes a first wiring extending along a first direction and having awiring width direction in a second direction perpendicular to the firstdirection, where stresses are generated inside, and second wiringselectrically connected to the first wiring and affected by the stressesof the first wiring, wherein end portions of the second wiringsconnected to the first wiring are bent parallel to a direction thatforms a predetermined angle with respect to the first direction.

A semiconductor device of claim 2 is the semiconductor device as definedin claim 1 wherein the end portions of the second wirings connected tothe first wiring are bent parallel to the second direction perpendicularto the first direction.

A semiconductor device of claim 3 includes a first wiring extendingalong a first direction and having a wiring width direction in a seconddirection perpendicular to the first direction, where stresses aregenerated inside, and second wirings electrically connected to endportions of the first wiring and affected by the stresses of the firstwiring, wherein end portions of the second wirings connected to thefirst wiring are disposed to extend along the first wiring and towardthe inside of the first wiring.

A semiconductor device of claim 4 includes a first wiring where stressesare generated inside, and second wirings electrically connected to thefirst wiring and affected by the stresses of the first wiring, whereinthe first wiring has a bent portion formed at its portion.

A semiconductor device of claim 5 is the semiconductor device as definedin claim 4 wherein a body of the first wiring, except end portionsconnected to the second wirings, is bent at a plurality of positions tohave a zigzag plan shape.

A semiconductor device of claim 6 is the semiconductor device as definedin claim 5 wherein the first wiring body comprises only oblique wiringparts parallel to directions, except a direction perpendicular to afirst direction, or only the oblique wiring parts and wiring partsparallel to the first direction.

A semiconductor device of claim 7 includes a first wiring extendingalong a first direction and having a wiring width direction in a seconddirection perpendicular to the first direction, where stresses aregenerated inside, and second wirings electrically connected to the firstwiring and affected by the stresses of the first wiring, wherein thewhole of the first wiring is divided into a plurality of wiring parts,and the respective wiring parts of the first wiring are electricallyconnected to form a predetermined current path extending from one end ofthe first wiring to the other end.

A semiconductor device of claim 8 includes a first wiring extendingalong a first direction and having a wiring width direction in a seconddirection perpendicular to the first direction, where stresses aregenerated inside, and second wirings electrically connected to the firstwiring and affected by the stresses of the first wiring, wherein thefirst wiring has narrow wiring width portions with narrower wiringwidths than those of the other portions, the narrow portions beingformed by chipping portions of a first wiring body, except end portionsthat are connected to the second wirings.

A semiconductor device of claim 9 is the semiconductor device as definedin claim 8 wherein the narrow wiring width portions are formed bychipping the first wiring body from the both sides at predeterminedpositions in the wiring path.

A semiconductor device of claim 10 is the semiconductor device asdefined in claim 9 wherein sides of the narrow wiring width portions areparallel to directions, except a direction perpendicular to the firstdirection.

A semiconductor device of claim 11 is the semiconductor device asdefined in claim 8 wherein the first wiring body has at least a firstnarrow wiring width portion that is formed by chipping the body from oneside, and at least a second narrow wiring width portion that is formedby chipping the body from the other side.

A semiconductor device of claim 12 is the semiconductor device asdefined in claim 11 wherein the wiring widths of the first and secondnarrow wiring width portions are smaller than 1/2 of those of theportions of the first wiring body, except the narrow wiring widthportions, and the current path along the center line of the first wiringis divided by the chipped parts at the first and second narrow wiringwidth portions.

A semiconductor device of claim 13 is the semiconductor device asdefined in claim 11 wherein sides of the first and second narrow wiringwidth portions at the chipped part sides are parallel to directions,except a direction perpendicular to the first direction.

A semiconductor device of claim 14 includes a first wiring extendingalong a first direction and having a wiring width direction in a seconddirection perpendicular to the first direction, where stresses aregenerated inside, and second wirings electrically connected to the firstwiring and affected by the stresses of the first wiring, wherein thefirst wiring has through openings formed in a first wiring body, exceptend portions connected to the second wirings.

A semiconductor device of claim 15 is the semiconductor device asdefined in claim 14 wherein the plan shapes of the through openings aremade a rectangular shape in which the length in the first direction issmaller than the length in the second direction perpendicular to thefirst direction.

A semiconductor device of claim 16 is the semiconductor device asdefined in any of claims 1 to 15 wherein the first wiring comprisesplatinum, iridium, titanium, or tungsten, and an insulating layercomprising a ferroelectric material is formed on the surface of thefirst wiring.

A semiconductor device of claim 17 constitutes a ferroelectric memorydevice with a plurality of memory cells comprising transistors andferroelectric capacitors, wherein the ferroelectric capacitor comprisesa first electrode where stresses are generated inside, a secondelectrode positioned opposite to this first electrode, and aferroelectric layer positioned between the first and second electrodes,the first electrode having a bent portion formed at its portion.

A semiconductor device of claim 18 constituting a ferroelectric memorydevice with a plurality of memory cells comprising transistors andferroelectric capacitors, wherein the ferroelectric capacitor comprisesa first electrode that extends along a first direction, where stressesare generated inside, a second electrode positioned opposite to thisfirst electrode, and a ferroelectric layer positioned between the firstand second electrodes, the whole of the first electrode being dividedinto a plurality of electrode parts, and the respective electrode partsbeing electrically connected to form a predetermined current pathextending from one end of the first electrode to the other end.

A semiconductor device of claim 19 is the semiconductor device asdefined in claim 17 wherein a body of the first electrode, except bothend portions, is bent at a plurality of positions to have a zigzag planshape.

A semiconductor device of claim 20 comprising as defined in claim 19 hasfirst and second memory cell groups each comprising a plurality ofmemory cells, first and second bit line groups corresponding to thefirst and second memory cell groups, first and second word line groupsprovided corresponding to the first and second memory cell groups, andcomprising a plurality of word lines for controlling ON and OFF oftransistors constituting the memory cells of the corresponding memorycell groups, and sense amplifiers connected to the respective bit linesof the first and second bit line groups, for sensing storage data on thebit lines. The first electrode of the ferroelectric capacitorconstituting each memory cell is connected to a cell plate line forapplying a predetermined driving voltage to the electrode. The secondelectrode of the ferroelectric capacitor constituting each memory cellof the first memory cell group is connected to the corresponding bitline of the first bit line group through the transistor of the firstmemory cell group. The second electrode of the ferroelectric capacitorconstituting each memory cell of the second memory cell group isconnected to the corresponding bit line of the second bit line groupthrough the transistor of the second memory cell group. The word line ofthe first word line group and the word line of the second word linegroup are simultaneously selected so that complementary data is read outonto the corresponding bit lines of both of the bit line groups.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1(a) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a first embodiment of thepresent invention, and

FIG. 1(b) is its cross-sectional view.

FIG. 2(a) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a second embodiment of thepresent invention, and

FIG. 2(b) is its cross-sectional view.

FIG. 3 is a plan view illustrating a wiring structure of a semiconductordevice in accordance with a third embodiment of the present invention.

FIG. 4 is a plan view illustrating a wiring structure of a semiconductordevice in accordance with a fourth embodiment of the present invention.

FIG. 5(a) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a fifth embodiment of thepresent invention, and

FIG. 5(b) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a modification example of thefifth embodiment.

FIG. 6 is a plan view illustrating a wiring structure of a semiconductordevice in accordance with a sixth embodiment of the present invention.

FIG. 7(a) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a seventh embodiment of thepresent invention, and

FIG. 7(b) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a modification example of theseventh embodiment.

FIG. 8(a) is a plan view illustrating a wiring structure of asemiconductor device in accordance with an eighth embodiment of thepresent invention,

FIG. 8(b) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a first modification example ofthe eighth embodiment, and

FIG. 8(c) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a second modification example ofthe eighth embodiment.

FIG. 9(a) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a ninth embodiment of thepresent invention, and

FIG. 9(b) is a plan view illustrating a wiring structure of asemiconductor device in accordance with a modification example of theninth embodiment.

FIG. 10 is a plan view illustrating a memory cell array of aferroelectric memory device in accordance with a tenth embodiment of thepresent invention.

FIG. 11(a) is a cross-sectional view of a part along a line XIa--XIashown in FIG. 10,

FIG. 11(b) is a cross-sectional view of a part along a line XIb--XIbshown in FIG. 10, and

FIG. 11(c) is a cross-sectional view of a part along a line XIc--XIcshown in FIG. 10.

FIG. 12(a) is a diagram for explaining an operation of the ferroelectricmemory device in accordance with the tenth embodiment of the invention,and

FIG. 12(b) is a diagram for explaining an operation of a ferroelectricmemory device in accordance with a modification example of the tenthembodiment.

FIG. 13(a) is a plan view illustrating a wiring structure of aconventional semiconductor device, FIG. 13(b) is its cross-sectionalview and

FIG. 13(c) shows another embodiment of its cross-sectional view.

FIG. 14 is a plan view illustrating a memory cell array of aconventional ferroelectric memory device.

FIG. 15(a) is a cross-sectional view of a part along a line XVa--XVashown in FIG. 14,

FIG. 15(b) is a cross-sectional view of a part along a line XVb--XVbshown in FIG. 14, and

FIG. 15(c) is a cross-sectional view of a part along a line XVc--XVcshown in FIG. 14.

BEST EMBODIMENTS FOR CARRYING OUT THE INVENTION

Embodiment 1

FIG. 1 is a diagram for explaining a semiconductor device according to afirst embodiment of the present invention. FIG. 1(a) is a plan viewillustrating a wiring structure of the semiconductor device, and FIG.1(b) is a cross-sectional view along a line Ib--Ib shown in FIG. 1(a).

In the figure, reference numeral 10 designates a wiring structure of asemiconductor device according to the first embodiment of the invention.This wiring structure 10 has a lower layer wiring (first wiring) 11 thatextends along a first direction D1 and has a wiring width direction in asecond direction perpendicular to the first direction D1, where tensilestresses (thermal stresses) are generated inside, and upper layerwirings (second wirings) 12a and 12b that are electrically connected tothe lower layer wiring 11 and are affected by the thermal stresses ofthe lower layer wiring 11.

In this case, the lower layer wiring 11 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an underlyinginsulating film 6. The upper layer wirings 12a and 12b are formed bypatterning an aluminum layer that is formed on the platinum layer via aninterlayer insulating film 7. The upper layer wirings 12a and 12b havestructures in which their end portions 12a₁ and 12b₂ are bentperpendicularly to bodies 12a₂ and 12b₂, except the end portions,respectively. The bodies 12a₂ and 12b₂ are located parallel to the lowerlayer wiring 11 extending along the first direction D1, and the bent endportions 12a₁ and 12b₁ are located parallel to the second direction D2perpendicular to the first direction D1.

The end portion 12a₁ of the upper layer wiring 12a is located on an endportion 11a of the lower layer wiring 11, and connected to the endportion 11a of the lower layer wiring 11 through a contact hole 7a thatis formed in the interlayer insulating film 7. The end portion 12b₁ ofthe upper layer wiring 12b is located on the other end portion 11b ofthe lower layer wiring 11, and connected to the other end portion 11b ofthe lower layer wiring 11 through a contact hole 7b that is formed inthe interlayer insulating film 7. In FIG. 1(a), the underlyinginsulating film 6 and the interlayer insulating film 7 are not shown.

In the first embodiment with such a construction, the end portions 12a₁and 12b₁ of the upper layer wirings 12a and 12b that are connected tothe lower layer wiring 11 are bent parallel to the second direction D2perpendicular to the first direction D1 along which the lower layerwiring 11 extends. Therefore, the end portions 12a₁ and 12b₁ of thesecond wirings are transformed by the tensile stresses in the firstdirection D1 being generated in the lower layer wiring 11, therebyreducing the stresses. Consequently, breaking of connection portions ofthe lower layer wiring 11 and the upper layer wirings 12a and 12b andportions of the upper layer wirings 12a and 12b due to the thermalstresses can be suppressed, resulting in improved reliability of thesemiconductor device.

In the first embodiment of the invention, the lower layer wiring 11formed by patterning the platinum layer that is formed on the insulatingfilm on the substrate surface is described. However, when a portion ofthe lower layer wiring 11 constitutes a lower electrode of aferroelectric capacitor or the like, the lower layer wiring 11 may beformed by patterning a platinum layer and a ferroelectric layer that aresuccessively formed on the insulating film on the substrate surface.That is, the lower layer wiring 11 may have a structure in which theferroelectric layer is formed on the surface of the platinum layerconstituting the lower layer wiring, except on the connection portionsof the upper layer wirings 12a and 12b.

In addition, in the first embodiment of the invention, as a multilayerwiring structure of the semiconductor device, the wiring structure 10shown in FIG. 1 is described. However, the semiconductor deviceaccording to the first embodiment may have the conventional wiringstructure 250 shown in FIG. 12, in addition to the wiring structure 10.For example, also in the semiconductor device of the first embodiment,when the influences by the thermal stresses of the lower layer wiring onother wirings connected to the lower layer wiring are small, forexample, the lower layer wiring is short, the conventional wiringstructure 250 can be employed as a multilayer wiring structure.

Embodiment 2

FIG. 2 is a diagram for explaining a semiconductor device according to asecond embodiment of the present invention. FIG. 2(a) is a plan viewillustrating a wiring structure of the semiconductor device, and FIG.2(b) is a cross-sectional view along a line IIb--IIb shown in FIG. 2(a).

In the figure, reference numeral 20 designates a wiring structure of asemiconductor device according to the second embodiment of theinvention. As in the first embodiment of the invention, this wiringstructure 20 has a lower layer wiring (first wiring) 11 that extendsalong a first direction D1, where tensile stresses (thermal stresses)are generated inside, and upper layer wirings (second wirings) 22a and22b that are electrically connected to the lower layer wiring 11 and areaffected by the thermal stresses of the lower layer wiring 11.

In this case, the upper layer wirings 22a and 22b are formed bypatterning an aluminum layer that is formed on a platinum layerconstituting the lower layer wiring 11 via an interlayer insulating film7. Further, the upper layer wiring 22a has a structure in which its endportion 22a₁ is bent perpendicularly to a body 22a₂, except the endportion. The body 22a₂ is located parallel to a second direction D2perpendicular to the first direction D1, and the bent end portion 22a₁extends parallel to the first direction D1 and toward the inside of thelower layer wiring 11. This end portion 22a₁ is located on an endportion 11a of the lower layer wiring 11, and connected to the endportion 11a of the lower layer wiring 11 through a contact hole 7a thatis formed in the interlayer insulating film 7.

The upper layer wiring 22b has a structure in which its end portion 22b₁is bent against a body 22b₂, except the end portion. The body 22b₂ islocated parallel to the first direction D1. The bent end portion 22b₁comprises a tip portion 22b₁₁ parallel to the first direction D1 and aportion 22b₁₂ parallel to the second direction D2 perpendicular to thefirst direction D1. The portion 22b₁₁ is located on the other endportion 11b of the lower layer wiring 11, and connected to the other endportion 11b of the lower layer wiring 11 through a contact hole 7b thatis formed in the interlayer insulating film 7. In FIG. 2(a), theunderlying insulating film 6 and the interlayer insulating film 7 arenot shown.

In the second embodiment with such a construction, the end portion 22a₁and the tip portion 22b₁₁ of the upper layer wirings 22a and 22b thatare connected to the lower layer wiring 11 are disposed along the lowerlayer wiring 11 and toward the inside of the lower layer wiring.Therefore, the body 22a₂ adjoining the end portion 22a₁ in the upperlayer wiring 22a, and the portion 22b₁₂ adjoining the tip portion 22b₁₁in the upper layer wiring 22b form predetermined angles with respect tothe first direction D1 along which the lower layer wiring 11 extends.Consequently, the body 22a₂ of the upper layer wiring 22a and theportion 22b₁₂ of the upper layer wiring 22b are transformed by thetensile stresses in the first direction D1 being generated in the lowerlayer wiring 11, thereby reducing the stresses. As a result, breaking ofconnection portions of the lower layer wiring 11 and the upper layerwirings 22a and 22b and the like due to the stresses can be suppressed,leading to improved reliability of the semiconductor device.

In the second embodiment of the invention, as a multilayer wiringstructure of the semiconductor device, the wiring structure 20 shown inFIG. 2 is described. However, the semiconductor device according to thesecond embodiment may have required one of the wiring structure 10 shownin FIG. 1 and the conventional wiring structure 250 shown in FIG. 12, inaddition to the wiring structure 20.

In addition, in the first and second embodiments of the invention,although the thermal stresses generated in the lower layer wiring 11 arereduced by the upper layer wirings connected to the lower layer wiring,the thermal stresses generated in the lower layer wiring may be reducedat the inside of the wiring. A wiring structure with such a constructionwill be described for a third embodiment.

Embodiment 3

FIG. 3 is a plan view for explaining a semiconductor device according toa third embodiment of the present invention, which illustrates a wiringstructure of the semiconductor device.

In the figure, reference numeral 30 designates a wiring structure of asemiconductor device according to the third embodiment of the invention,and its cross-sectional structure is identical to the wiring structure250 of the conventional semiconductor device. This wiring structure 30has a lower layer wiring (first wiring) 31 where tensile stresses(thermal stresses) are generated inside, and upper layer wirings (secondwirings) 2a and 2b that are electrically connected to the lower layerwiring 31 and are affected by the thermal stresses of the lower layerwiring 31.

In this case, the lower layer wiring 31 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm. An end portion 31a of the lower layer wiring is connected to anend portion 2a₁ of the upper layer wiring 2a through a contact hole 7athat is formed in an interlayer insulating film, and the other endportion 31b is connected to an end portion 2b₁ of the upper layer wiring2b through a contact hole 7b that is formed in the interlayer insulatingfilm.

Further, the lower layer wiring 31 has two bent portions 32a and 32b inthe center of the position between the contact holes 7a and 7b. Morespecifically, the lower layer wiring 31 comprises a first lateral sideportion 31c that extends from the end portion 31a to the center of thewiring along the first direction D1, a second lateral side portion 31dthat extends from the other end portion 31b to the center of the wiringalong the first direction D1, and is parallel to the first lateral sideportion 31c, and a longitudinal side portion 31e that is located in thecenter of the lower layer wiring 31, adjoins the lateral side portions31c and 31d, and is parallel to a second direction D2 perpendicular tothe first direction D1. A connection portion of the longitudinal sideportion 31e and the first lateral side portion 31c, and a connectionportion of the longitudinal side portion 31e and the second lateral sideportion 31d are the bent portions 32a and 32b, respectively. The otherconstruction is identical to the conventional wiring structure 250.

In the third embodiment of the invention with such a construction, thelower layer wiring 31 in which the tensile stresses are generated hasthe two bent portions 32a and 32b in the center. Therefore, the bentportions are transformed by the tensile stresses being generated in thelongitudinal direction D1 of the lower layer wiring 31, thereby reducingthe tensile stresses. As a result, breaking of connection portions ofthe lower layer wiring 31 and the upper layer wirings 2a and 2b,portions of the upper layer wirings and the like due to the stresses canbe suppressed, leading to improved reliability of the semiconductordevice.

In addition, in the third embodiment of the invention, as a multilayerwiring structure of the semiconductor device, the wiring structure 30shown in FIG. 3 is described. However, the semiconductor deviceaccording to the third embodiment may have required one of the wiringstructure 10 shown in FIG. 1, the wiring structure 20 shown in FIG. 2,and the conventional wiring structure 250 shown in FIG. 12, in additionto the wiring structure 30.

Embodiment 4

FIG. 4 is a plan view for explaining a semiconductor device according toa fourth embodiment of the present invention, which illustrates a wiringstructure of the semiconductor device.

In the wiring structure according to the fourth embodiment, tensilestresses generated in a lower layer wiring (first wiring) are reduced ata bent portion of the lower layer wiring, and the influences by thestresses on the upper layer wiring are reduced by means of the directionof leading an upper layer wiring (second wiring) to which the tensilestresses (thermal stresses) are applied. In principle, this wiringstructure is obtained by combining the wiring structure 10 of the firstembodiment and the wiring structure 20 of the second embodiment.

A brief description is given using FIG. 4. In the figure, referencenumeral 40 designates a wiring structure of a semiconductor deviceaccording to the fourth embodiment of the invention. The same referencenumerals as those shown in FIGS. 1 and 3 designate the same parts in thefirst and third embodiments.

This wiring structure 40 has a lower layer wiring (first wiring) 41where tensile stresses (thermal stresses) are generated, and upper layerwirings (second wirings) 12a and 2b that are electrically connected tothe lower layer wiring 41 and are affected by the thermal stresses ofthe lower layer wiring 41. In this case, the lower layer wiring 41 isformed by patterning a platinum layer that is formed on a siliconsubstrate 5 via an insulating film. The upper layer wirings 12a and 2bare formed by patterning an aluminum layer that is formed on theplatinum layer via an interlayer insulating film. The upper layer wiring12a has a structure in which its end portion 12a₁ is bentperpendicularly to a body 12a₂, except the end portion.

The end portion 12a₁ of the upper layer wiring 12a is located on an endportion 41a of the lower layer wiring 41, and connected to the endportion 41a of the lower layer wiring 41 through a contact hole 7a thatis formed in the interlayer insulating film. An end portion 2b₁ of theupper layer wiring 2b is located on the other end portion 41b of thelower layer wiring 41, and connected to the end portion 41b of the lowerlayer wiring 41 through a contact hole 7b that is formed in theinterlayer insulating film.

Further, the lower layer wiring 41 has a bent portion 42a in a region atthe vicinity of the both contact hole 7b. More specifically, the lowerlayer wiring 41 comprises a lateral side portion 41c that extends fromthe end portion 41a to the vicinity of the other end portion 41b alongthe first direction D1, and a longitudinal side portion 41d that extendsfrom the other end portion 41b along a second direction D2 perpendicularto the first direction D1, and adjoins the lateral side portion 41c. Aconnection portion of the longitudinal side portion 41d and the lateralside portion 41c is the bent portion 42a.

In the fourth embodiment with such a construction, the tensile stressesthat are applied to the upper layer wiring 12a are reduced by thetransformation of the bent portion 12a₁ of the wiring 12a, and thetensile stresses that are applied to the upper layer wiring 2b arereduced by the transformation of the bent portion 42a of the lower layerwiring 41. As a result, as in the respective embodiments, breaking ofconnection portions of the lower layer wiring 41 and the upper layerwirings 12a and 2b, portions of the upper layer wirings and the like dueto the tensile stresses being generated in the lower layer wiring 41 canbe suppressed, leading to improved reliability of the semiconductordevice.

In the fourth embodiment of the invention, although the lower layerwiring 41 has one bent portion, the lower layer wiring may have bentportions at two positions.

In addition, in the fourth embodiment of the invention, there isdescribed the structure that is obtained by combining the structure ofthe upper layer wiring according to the first embodiment and thestructure of the lower layer wiring according to the third embodiment.However, a wiring structure in which stresses of a lower layer wiringare reduced may be realized by combining the structure of the lowerlayer wiring according to the first embodiment and the structure of theupper layer wiring according to the second embodiment.

Further, in the fourth embodiment of the invention, as a multilayerwiring structure of the semiconductor device, the wiring structure 40shown in FIG. 4 is described. However, the semiconductor deviceaccording to the fourth embodiment may have required one of the wiringstructure 10 shown in FIG. 1, the wiring structure 20 shown in FIG. 2,the wiring structure 30 shown in FIG. 3, and the conventional wiringstructure 250 shown in FIG. 12, in addition to the wiring structure 40.

Embodiment 5

FIG. 5 is a plan view for explaining a semiconductor device according toa fifth embodiment of the present invention, each of which illustrates awiring structure of the semiconductor device.

This wiring structure shown in FIG. 5 is obtained by developing thewiring structure 30 of the third embodiment, and has a structure inwhich the lower layer wiring 31 has bent portions at six positions,thereby reducing tensile stresses generated in a lower layer wiring moreeffectively. In addition, in the lower layer wiring with such aconstruction, when the distance between contact holes 7a and 7b in thefirst direction D1 is constant, the wiring is longer than the lowerlayer wirings in the respective embodiments.

A brief description is given using FIG. 5. In the figure, referencenumeral 50 designates a wiring structure of a semiconductor deviceaccording to the fifth embodiment of the invention, and itscross-sectional structure is identical to the wiring structure 250 ofthe conventional semiconductor device.

This wiring structure 50 has a lower layer wiring (first wiring) 51where tensile stresses are generated inside, and upper layer wirings(second wirings) 2a and 2b that are electrically connected to the lowerlayer wiring 51 and are affected by the thermal stresses of the lowerlayer wiring 51. An end portion 2a₁ of the upper layer wiring 2a islocated on an end portion 51a of the lower layer wiring 51, andconnected to the end portion 51a of the lower layer wiring 51 through acontact hole 7a that is formed in an interlayer insulating film, and anend portion 2b₁ of the upper layer wiring 2b is located on the other endportion 51b of the lower layer wiring 51, and connected to the other endportion 51b of the lower layer wiring 51 through a contact hole 7b thatis formed in the interlayer insulating film.

In this case, the lower layer wiring 51 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm, and has six bent portions 52a˜52f in a region between the contactholes 7a and 7b. More specifically, a body 51c of the lower layer wiring51, except the both end portions 51a and 51b, comprises first to fourthlateral side portions 51c₁₁ ˜51c₁₄ parallel to the first direction D1,and first to third longitudinal side portions 51c₂₁ ˜51c₂₃ parallel to asecond direction D2 perpendicular to the first direction D1, and has astructure in which the lateral side portions and the longitudinal sideportions are alternately connected. Connection portions of the adjacentlateral side portions and longitudinal side portions are the bentportions 52a˜52f, respectively. As a result, the lower layer wiring 51has a zigzag-shaped plan as a whole.

The ratio of the length L₅₁ of the lower layer wiring 51 between thecontact holes 7a and 7b to the swinging width W₅₁ of the zigzag shape(L₅₁ /W₅₁) is 2. This is because it has been ascertained from theresults of experiments that the effect of reducing stresses isremarkable under the condition that the ratio (L₅₁ /W₅₁) satisfies arelationship of L₅₁ /W₅₁ ≦10.

In the fifth embodiment with such a construction, the lower layer wiring51 has more bent portions 52a˜52f than those of the lower layer wiring31 of the third embodiment. Therefore, the tensile stresses in thelateral direction of the lower layer wiring are reduced by thetransformation of the six bent portions. As a result, as compared withthe third embodiment, the reduction in stresses can be realized moresatisfactory.

In addition, it is possible to combine the structure of the zigzag lowerlayer wiring 51 and the structure of the upper layer wirings accordingto the first or second embodiment. In this case, production of thebreaking of the upper layer wirings due to the tensile stresses and thelike can be suppressed more effectively.

Further, the zigzag shape of the body 51c of the lower layer wiring 51is not always a shape in which the lateral side portions are parallel tothe first direction and the longitudinal side portions are parallel tothe second direction as shown in FIG. 5(a).

FIG. 5(b) illustrates a wiring structure according to a modificationexample of the fifth embodiment of the invention. In the wiringstructure of this modification example, in place of the longitudinalside portions 51c₂₁ ˜51c₂₃ of the lower layer wiring 51 of the fifthembodiment, a lower layer wiring has a plurality of oblique sideportions parallel to a direction between first and second directions.

In FIG. 5(b), reference numeral 55 designates a wiring structure of asemiconductor device according to a modification example of the fifthembodiment. The same reference numerals as those shown in FIG. 5(a)designate the same parts in the fifth embodiment.

This wiring structure 55 has a lower layer wiring (first wiring) 56where tensile stresses (thermal stresses) are generated inside, andupper layer wirings (second wirings) 2a and 2b that are electricallyconnected to the lower layer wiring 56 and are affected by the thermalstresses of the lower layer wiring 56. An end portion 2a₁ of the upperlayer wiring 2a is located on an end portion 56a of the lower layerwiring 56, and connected to the end portion 56a of the lower layerwiring 56 through a contact hole 7a that is formed in an interlayerinsulating film, and an end portion 2b₁ of the upper layer wiring 2b islocated on the other end portion 56b of the lower layer wiring 56, andconnected to the other end portion 56b of the lower layer wiring 56through a contact hole 7b that is formed in the interlayer insulatingfilm.

In this case, the lower layer wiring 56 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm, and has eight bent portions 57a˜57h in a region between thecontact holes 7a and 7b. More specifically, a body 56c of the lowerlayer wiring 56 comprises first to fifth lateral side portions 56c₁₁˜56c₁₅ parallel to the first direction D1, second and third longitudinalside portions 56c₂₂ and 56c₂₃ parallel to a direction that forms anangle of about +45° with respect to the first direction D1, and firstand fourth longitudinal side portions 56c₂₁ and 56c₂₄ parallel to adirection that forms an angle of about -45° with respect to the firstdirection D1, and has a structure in which the lateral side portions andthe oblique side portions are alternately connected. Connection portionsof the adjacent lateral side portions and oblique side portions are thebent portions 57a˜57h, respectively. As a result, the lower layer wiring56 has a zigzag-shaped plan as a whole.

In the modification example of the fifth embodiment with such aconstruction, the lower layer wiring 56 having the zigzag plan shape isconstituted by alternately arranging the lateral side portions parallelto the first direction D1 and the oblique side portions that form anglesof 45° with respect to the first direction. Therefore, the size of thelower layer wiring 56 having the zigzag plan shape in the seconddirection D2 perpendicular to the first direction D1 is reduced. As aresult, the area of the lower layer wiring 56 on the substrate can bereduced, as compared with the area in the fifth embodiment.

In addition, in the fifth embodiment of the invention, as a multilayerwiring structure of the semiconductor device, the wiring structure 50shown in FIG. 5(a) and the wiring structure 55 as a modification exampleof the structure 50 (refer to FIG. 5(b)) are described. However, thesemiconductor devices according to the fifth embodiment and itsmodification example may have required one of the wiring structures 10,20, 30 and 40 described for the first to fourth embodiments, and theconventional wiring structure 250 shown in FIG. 12, in addition to thewiring structures 50 and 55. Further, as another modification example ofthe fifth embodiment, a structure having both of the wiring structures50 and 55 can be also considered.

Embodiment 6

FIG. 6 is a plan view for explaining a semiconductor device according toa sixth embodiment of the present invention, which illustrates a wiringstructure of the semiconductor device.

In this wiring structure shown in FIG. 6, a lower layer wiring isdivided into a plurality of wiring parts, and the wiring parts areconnected through other wirings, thereby dispersing and reducing tensilestresses generated in the lower layer wiring. In this case, the lengthof the lower layer wiring and its tensile stresses basically have aproportional relationship, and it is necessary to determine the lengthsof the wiring parts into which the lower layer wiring is divided, in apermissible range of the stresses.

A brief description is given using FIG. 6. In the figure, referencenumeral 60 designates a wiring structure of a semiconductor deviceaccording to the sixth embodiment of the invention, and itscross-sectional structure is identical to the wiring structure 250 ofthe conventional semiconductor device.

This wiring structure 60 has a lower layer wiring (first wiring) 61 thatextends along a first direction D1 and has a wiring width direction in asecond direction perpendicular to the first direction D1, where tensilestresses (thermal stresses) are generated inside, and upper layerwirings (second wirings) 2a and 2b that are electrically connected tothe lower layer wiring 61 and are affected by the thermal stresses ofthe lower layer wiring 61.

In this case, the lower layer wiring 61 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm, and has a structure in which the whole is divided into two wiringparts, i.e., first and second wiring parts 61a and 61b, and these partsare electrically connected through a connecting wiring 2c.

The upper layer wirings 2a and 2b and the connecting wiring 2c areformed by patterning an aluminum layer that is formed on the platinumlayer via an interlayer insulating film. An end portion 2a₁ of the upperlayer wiring 2a is located on an end portion 61a₁ of the first wiringpart 61a, and connected to the end portion 61a₁ through a contact hole7a that is formed in the interlayer insulating film. An end portion 2b₁of the upper layer wiring 2b is located on the other end portion 61b₂ ofthe second wiring part 61b and connected to the other end portion 61b₂through a contact hole 7b that is formed in the interlayer insulatingfilm. The upper layer wiring 2a extends from the contact hole 7a to adirection opposite toward the first direction D1 along the firstdirection, and the upper layer wiring 2b extends from the contact hole7b toward the first direction D1 along this direction.

An end portion 2c₁ of the upper layer wiring 2c is located on the otherend portion 61a₂ of the first wiring part 61a and connected to the otherend portion 61a₂ through a contact hole 7c that is formed in theinterlayer insulating film. An end portion 2c₂ of the upper layer wiring2c is located on an end portion 61b₁ of the second wiring part 61b andconnected to the end portion 61b₁ through a contact hole 7d that isformed in the interlayer insulating film.

In the sixth embodiment with such a construction, the lower layer wiring61 in which the thermal stresses are generated has a structure in whichthe whole is divided into the two wiring parts 61a and 61b. Therefore,the thermal stresses in the lower layer wiring 61 are dispersed, therebyreducing the thermal stresses that are applied to the upper layerwirings 2a and 2b.

In addition, it has been ascertained from experiments and the like thatwhen the ratio of the wiring length L₆₁ of the first or second wiringpart to the wiring width W₆₁ (L₆₁ /W₆₁) satisfies L₆₁ /W₆₁ ≦20, theeffect of reducing stresses is remarkable. By setting each wiring partto the ratio in size described above, the thermal stresses in the lowerlayer wiring can be reduced effectively. Further, by making the planshape of each wiring part a zigzag plan shape as shown in FIG. 5, theratio of the wiring length to the wiring width (L₆₁ /W₆₁) can be madelarger.

In the sixth embodiment of the invention, it is not required to formbent portions in the lower layer wiring 61 and the upper layer wirings2a and 2b. Accordingly, the wiring structure 60 can be realized in anarrow region on the substrate, thereby reducing the occupied area onthe substrate, as compared with the respective embodiments.

It is possible to combine the structure of the lower layer wiringaccording to the sixth embodiment, with the structure of the upper layerwirings according to the first or second embodiment or the structure ofthe lower layer wiring according to the third or fifth embodiment.

Further, in the sixth embodiment of the invention, there is described acase in which the upper layer wirings 2a and 2b and the connectingwiring 2c are formed by patterning the identical aluminum layer that isformed on the interlayer insulating film. However, the upper layerwirings 2a and 2b and the connecting wiring 2c may be formed bypatterning different aluminum layers.

Furthermore, in the sixth embodiment of the invention, as a multilayerwiring structure of the semiconductor device, the wiring structure 60shown in FIG. 6 is described. However, the semiconductor deviceaccording to the sixth embodiment may have required one of the wiringstructures 10, 20, 30, 40, 50 and 55 described for the first to fifthembodiments, and the conventional wiring structure 250 shown in FIG. 12,in addition to the wiring structure 60.

Embodiment 7

FIG. 7 is a diagram for explaining a semiconductor device according to aseventh embodiment of the present invention, and FIG. 7(a) illustrates awiring structure of the semiconductor device according to the seventhembodiment.

In the figure, reference numeral 70 designates a wiring structure of asemiconductor device according to the seventh embodiment of theinvention, and its cross-sectional structure is identical to theconventional wiring structure. This wiring structure 70 has a lowerlayer wiring (first wiring) 71 that extends along a first direction D1and has a wiring width direction in a second direction perpendicular tothe first direction D1, where tensile stresses (thermal stresses) aregenerated, and upper layer wirings (second wirings) 2a and 2b that areelectrically connected to the lower layer wiring 71 and are affected bythe thermal stresses of the lower layer wiring 71. An end portion 2a₁ ofthe upper layer wiring 2a is located on an end portion 71a of the lowerlayer wiring 71, and connected to the end portion 71a of the lower layerwiring 71 through a contact hole 7a that is formed in an interlayerinsulating film. An end portion 2b₁ of the upper layer wiring 2b islocated on the other end portion 71b of the lower layer wiring 71, andconnected to the end portion 71b of the lower layer wiring 71 through acontact hole 7b that is formed in the interlayer insulating film.

In this case, the lower layer wiring 71 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm, and has narrow wiring width portions 71c₁₀, 71c₂₀, 71c₃₀ and 71c₄₀with narrower wiring widths than those of the other portions, the narrowportions being formed by chipping portions of a body 71c, except the endportions 71a and 71b connected to the upper layer wirings 2a and 2b. Thenarrow wiring width portions 71c₁₀ ˜71c₄₀ are formed by chipping thebody 71c of the lower layer wiring 71 at from both sides atpredetermined positions in the wiring path. Reference characters 71c₁₁,71c₂₂, 71c₃₃ and 71c₄₄ designate chipped parts of rectangular shapes atthe respective narrow wiring width portions 71c₁₀ ˜71c₄₀.

In the seventh embodiment with such a construction, the lower layerwiring 71 in which the thermal stresses are generated has the narrowwiring width portions 71c₁₀ ˜71c₄₀ with narrower wiring widths thanthose of the other portions, at its portions. Therefore, the lower layerwiring 71 is probable to be transformed by stretching at the narrowwiring width portions, whereby the thermal stresses generated in thelower layer wiring 71 are satisfactorily reduced by the transformationof the narrow wiring width portions. Consequently, breaking of the upperlayer wirings 2a and 2b, connection portions of the upper layer wiringsand the lower layer wiring 71 and the like due to the tensile stressesbeing generated in the lower layer wiring 71 can be suppressed, leadingto improved reliability of the semiconductor device.

In addition, the shape of the chipped part at each narrow wiring widthportion of the lower layer wiring is not always a rectangular shape asshown in FIG. 7(a).

For example, FIG. 7(b) illustrates a wiring structure according to amodification example of the seventh embodiment of the invention. In thiswiring structure, the shape of a chipped part at each narrow wiringwidth portion of a lower layer wiring is a V shape.

More specifically, in FIG. 7(b), reference numeral 75 designates awiring structure of a semiconductor device according to a modificationexample of the seventh embodiment. The same reference numerals as thoseshown in FIG. 7(a) designate the same parts as the wiring structure 70in the seventh embodiment.

This wiring structure 75 has a lower layer wiring (first wiring) 76 thatextends along a first direction D1 and has a wiring width direction in asecond direction perpendicular to the first direction D1, where tensilestresses (thermal stresses) are generated, and upper layer wirings(second wirings) 2a and 2b that are electrically connected to the lowerlayer wiring 76 and are affected by the thermal stresses of the lowerlayer wiring 76. An end portion 2a₁ of the upper layer wiring 2a islocated on an end portion 76a of the lower layer wiring 76, andconnected to the end portion 76a of the lower layer wiring 76 through acontact hole 7a that is formed in an interlayer insulating film. An endportion 2b₁ of the upper layer wiring 2b is located on the other endportion 76b of the lower layer wiring 76, and connected to the endportion 76b of the lower layer wiring 76 through a contact hole 7b thatis formed in the interlayer insulating film.

In this case, the lower layer wiring 76 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm, and has narrow wiring width portions 76c₁₀, 76c₂₀, 76c₃₀ and 76c₄₀with narrower wiring widths than those of the other portions, the narrowportions being formed by chipping portions of a body 76c, except the endportions 76a and 76b connected to the upper layer wirings 2a and 2b. Thenarrow wiring width portions 76c₁₀ ˜76c₄₀ are formed by chipping thebody 76c of the lower layer wiring 76 from both sides at predeterminedpositions in the wiring path. Reference characters 76c₁₁, 76c₂₂, 76c₃₃and 76c₄₄ designate chipped parts of V shapes at the respective narrowwiring width portions 76c₁₀ ˜76c₄₀.

In the modification example of the seventh embodiment with such aconstruction, the shapes of the chipped parts 76c₁₁ ˜76c₄₄ of the narrowwiring width portions 76c₁₀ ˜76c₄₀ are V shapes. Therefore, as comparedwith the chipped parts 71c₁₁ ˜71c₄₄ of rectangular shapes according tothe seventh embodiment, the areas of the chipped parts in the lowerlayer wiring 76 can be reduced, whereby it is more advantageous whenelements, such as capacitors, are disposed on the lower layer wiring 76.

In the seventh embodiment of the invention, as a multilayer wiringstructure of the semiconductor device, the wiring structure 70 shown inFIG. 7(a) and the wiring structure 75 as a modification example of thestructure 70 (refer to FIG. 7(b)) are described. However, thesemiconductor devices according to the seventh embodiment and itsmodification example may have required one of the wiring structures 10,20, 30, 40, 50, 55 and 60 described for the first to sixth embodiments,and the conventional wiring structure 250 shown in FIG. 12, in additionto the wiring structures 70 and 75. Further, as another modificationexample of the seventh embodiment, a structure having both of the wiringstructures 70 and 75 can be also considered.

Embodiment 8

FIG. 8 is a diagram for explaining a semiconductor device according toan eighth embodiment of the present invention, and FIG. 8(a) illustratesa wiring structure of the semiconductor device according to the eighthembodiment.

In the figure, reference numeral 80 designates a wiring structure of asemiconductor device according to the eighth embodiment of theinvention, and its cross-sectional structure is identical to theconventional wiring structure.

This wiring structure 80 has a lower layer wiring (first wiring) 81 thatextends along a first direction D1 and has a wiring width direction in asecond direction perpendicular to the first direction D1, where tensilestresses (thermal stresses) are generated, and upper layer wirings(second wirings) 2a and 2b that are electrically connected to the lowerlayer wiring 81 and are affected by the thermal stresses of the lowerlayer wiring 81.

In this case, the lower layer wiring 81 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm. A body 81c, except end portions 81a and 81b that are connected tothe upper layer wirings 2a and 2b, has first narrow wiring widthportions 81c₁₀ and 81c₃₀ with narrower wiring widths than those of theother portions, the narrow portions being formed by chipping one side ofthe body 81c, and second narrow wiring width portions 81c₂₀ and 81c₄₀with narrower wiring widths than those of the other portions, the narrowportions being formed by chipping the other side of the body 81c. Thefirst narrow wiring width portions 81c₁₀ and 81c₃₀, and the secondnarrow wiring width portions 81c₂₀ and 81c₄₀ are alternately arrangedalong the first direction D1. Reference characters 81c₁₁, 81c₂₂, 81c₃₃and 81c₄₄ designate chipped parts of rectangular shapes at therespective narrow wiring width portions 81c₁₀ ˜81c₄₀.

In the eighth embodiment with such a construction, the lower layerwiring 81 in which the thermal stresses are generated has the narrowwiring width portions 81c₁₀ ˜81c₄₀ with narrower wiring widths thanthose of the other portions, at its portions. Therefore, the lower layerwiring 81 can be easily transformed by stretching at the narrow wiringwidth portions, whereby the thermal stresses generated in the lowerlayer wiring 81 are satisfactorily reduced by the transformation of thenarrow wiring width portions. Consequently, breaking of the upper layerwirings 2a and 2b, connection portions of the upper layer wirings andthe lower layer wiring 81 and the like due to the tensile stresses beinggenerated in the lower layer wiring 81 can be suppressed, leading toimproved reliability of the semiconductor device.

Further, in the eighth embodiment of the invention, the chipped parts81c₁₁ and 81c₃₃ at one side of the lower layer wiring 81, and thechipped parts 81c₂₂ and 81c₄₄ at the other side of the lower layerwiring 81 are alternately arranged along the wiring path. Therefore, thelower layer wiring 81 is transformed by stretching at the narrow wiringwidth portions 81c₁₀ ˜81c₄₀ due to the tensile stresses, as well as thechipped parts 81c₁₁ ˜81c₄₄ are transformed by curving so that theiropenings become wider. Accordingly, by the transformation by stretchingand the transformation by curving, the tensile stresses in the lowerlayer wiring are exceedingly reduced. As a result, production ofbreaking of the upper layer wirings 2a and 2b connected to the lowerlayer wiring 81, connection portions of the lower layer wiring and theupper layer wirings and the like can be exceedingly reduced.

In addition, the shape of the chipped part at each narrow wiring widthportion of the lower layer wiring is not always a rectangular shape asshown in FIG. 8(a).

FIG. 8(b) illustrates a wiring structure according to a firstmodification example of the eighth embodiment of the invention. In thiswiring structure, the shape of a chipped part at each narrow wiringwidth portion of a lower layer wiring is a V shape.

More specifically, in FIG. 8(b), reference numeral 85 designates awiring structure of a semiconductor device according to a firstmodification example of the eighth embodiment. The same referencenumerals as those shown in FIG. 8(a) designate the same parts as thewiring structure 80 in the eighth embodiment.

This wiring structure 85 has a lower layer wiring (first wiring) 86 thatextends along a first direction D1 and has a wiring width direction in asecond direction perpendicular to the first direction D1, where tensilestresses (thermal stresses) are generated, and upper layer wirings(second wirings) 2a and 2b that are electrically connected to the lowerlayer wiring 86 and are affected by the thermal stresses of the lowerlayer wiring 86. An end portion 2a₁ of the upper layer wiring 2a islocated on an end portion 86a of the lower layer wiring 86, andconnected to the end portion 86a of the lower layer wiring 86 through acontact hole 7a that is formed in an interlayer insulating film. An endportion 2b₁ of the upper layer wiring 2b is located on the other endportion 86b of the lower layer wiring 86, and connected to the endportion 86b of the lower layer wiring 86 through a contact hole 7b thatis formed in the interlayer insulating film.

In this case, the lower layer wiring 86 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm. A body 86c of this lower layer wiring 86, except the end portions86a and 86b connected to the upper layer wirings 2a and 2b, has firstnarrow wiring width portions 86c₁₀ and 86c₃₀ with narrower wiring widthsthan those of the other portions, the narrow portions being formed bychipping one side of the body 86c, and second narrow wiring widthportions 86c₂₀ and 86c₄₀ with narrower wiring widths than those of theother portions, the narrow portions being formed by chipping the otherside of the body 86c. The first narrow wiring width portions 86c₁₀ and86c₃₀, and the second narrow wiring width portions 86c₂₀ and 86c₄₀ arealternately arranged along the first direction D1. Reference characters86c₁₁, 86c₂₂, 86c₃₃ and 86c₄₄ designate chipped parts of V shapes at therespective narrow wiring width portions 86c₁₀ ˜86c₄₀.

In the modification example of the eighth embodiment with such aconstruction, the shapes of the chipped parts 86c₁₁ ˜86c₄₄ of the narrowwiring width portions 86c₁₀ ˜86c₄₀ are V shapes. Therefore, as comparedwith the chipped parts 81c₁₁ ˜81c₄₄ of rectangular shapes according tothe eighth embodiment, the areas of the chipped parts in the lower layerwiring 86 can be reduced. It is more advantageous when elements, such ascapacitors, are disposed on the lower layer wiring 86.

FIG. 8(c) illustrates a wiring structure according to a secondmodification example of the eighth embodiment of the invention. In thiswiring structure, wiring widths of first and second narrow wiring widthportions of a lower layer wiring are smaller than 1/2 of wiring widthsof portions of the lower layer wiring body, except the narrow wiringwidth portions.

More specifically, in FIG. 8(c), reference numeral 87 designates awiring structure of a semiconductor device according to a secondmodification example of the eighth embodiment. The same referencenumerals as those shown in FIG. 8(a) designate the same parts as thewiring structure 80 in the eighth embodiment.

This wiring structure 87 has a lower layer wiring (first wiring) 88 thatextends along a first direction D1 and has a wiring width direction in asecond direction perpendicular to the first direction D1, where tensilestresses (thermal stresses) are generated, and upper layer wirings(second wirings) 2a and 2b that are electrically connected to the lowerlayer wiring 88 and are affected by the thermal stresses of the lowerlayer wiring 88. An end portion 2a₁ of the upper layer wiring 2a islocated on an end portion 88a of the lower layer wiring 88, andconnected to the end portion 88a of the lower layer wiring 88 through acontact hole 7a that is formed in an interlayer insulating film. An endportion 2b₁ of the upper layer wiring 2b is located on the other endportion 88b of the lower layer wiring 88, and connected to the endportion 88b of the lower layer wiring 88 through a contact hole 7b thatis formed in the interlayer insulating film.

In this case, the lower layer wiring 88 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm. A body 88c of this lower layer wiring 88, except the end portions88a and 88b connected to the upper layer wirings 2a and 2b, has firstnarrow wiring width portions 88c₁₀ and 88c₃₀ with narrower wiring widthsthan those of the other portions, the narrow portions being formed bychipping one side of the body 88c, and second narrow wiring widthportions 88c₂₀ and 88c₄₀ with narrower wiring widths than those of theother portions, the narrow portions being formed by chipping the otherside of the body 88c. The first narrow wiring width portions 88c₁₀ and88c₃₀, and the second narrow wiring width portions 88c₂₀ and 88c₄₀ arealternately arranged along the first direction D1. The wiring widths ofthe respective narrow wiring width portions 88c₁₀ ˜88c₄₀ are smallerthan 1/2 of the wiring widths of portions of the wiring body 88c, exceptthe narrow wiring width portions. In other words, the current path alongthe center line of the lower layer wiring 88 is divided into parts bychipped parts 88c₁₁, 88c₂₂, 88c₃₃ and 88c₄₄ of rectangular shapes at therespective narrow wiring width portions 88c₁₀, 88c₂₀, 88c₃₀ and 88c₄₀.

In the second modification example of the eighth embodiment with such aconstruction, the wiring widths of the respective narrow wiring widthportions 88c₁₀ ˜88c₄₀ are smaller than 1/2 of the wiring widths ofportions of the wiring body 88c, except the narrow wiring widthportions. Therefore, in the narrow wiring width portions at which thechipped parts are formed, there occurs not only transformation bystretching but transformation by curving due to the thermal stresses ofthe lower layer wiring. As a result, as compared with the narrowportions of the eighth embodiment, the narrow wiring width portions canbe very easily transformed by the thermal stresses of the lower layerwiring, whereby breaking of the upper layer wirings and connectionportions of the upper layer wirings and the lower layer wiring due tothe thermal stresses can be further suppressed.

In addition, in the eighth embodiment of the invention, as a multilayerwiring structure of the semiconductor device, the wiring structure 80shown in FIG. 8(a), the wiring structure 85 as a first modificationexample of the structure 80 (refer to FIG. 8(b)), and the wiringstructure 87 as a second modification example of the structure 80 (referto FIG. 8(c)) are described. However, the semiconductor devicesaccording to the eighth embodiment and its first and second modificationexamples may have required one of the wiring structures 10, 20, 30, 40,50, 55, 60, 70 and 75 described for the first to seventh embodiments,and the conventional wiring structure 250 shown in FIG. 12, in additionto the wiring structures 80, 85 and 87. Further, as another modificationexample of the eighth embodiment, a structure having two of the wiringstructures 80, 85 and 87 or all of these three wiring structures can bealso considered.

Embodiment 9

FIG. 9 is a diagram for explaining a semiconductor device according to aninth embodiment of the present invention, and FIG. 9(a) illustrates awiring structure of the semiconductor device according to the ninthembodiment.

In the figure, reference numeral 90 designates a wiring structure of asemiconductor device according to the ninth embodiment of the invention,and its cross-sectional structure is identical to the conventionalwiring structure 250.

This wiring structure 90 has a lower layer wiring (first wiring) 91 thatextends along a first direction D1 and has a wiring width direction in asecond direction perpendicular to the first direction D1, where tensilestresses are generated inside, and upper layer wirings (second wirings)2a and 2b that are electrically connected to the lower layer wiring 91and are affected by the thermal stresses of the lower layer wiring 91.An end portion 2a₁ of the upper layer wiring 2a is located on an endportion 91a of the lower layer wiring 91, and connected to the endportion 91a of the lower layer wiring 91 through a contact hole 7a thatis formed in an interlayer insulating film. An end portion 2b₁ of theupper layer wiring 2b is located on the other end portion 91b of thelower layer wiring 91, and connected to the end portion 91b of the lowerlayer wiring 91 through a contact hole 7b that is formed in theinterlayer insulating film.

In this case, the lower layer wiring 91 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm. A body 91c, except the end portions 91a and 91b connected to theupper layer wirings 2a and 2b, has a plurality of through openings 91c₁˜91c₄ at predetermined intervals along the first direction D1. Thesethrough openings 91c₁ ˜91c₄ have rectangular shapes, and itslongitudinal direction matches with the first direction D1.

In the ninth embodiment with such a construction, the lower layer wiring91 in which the thermal stresses are generated has the plurality ofthrough openings 91c₁ ˜91c₄ that are disposed along the longitudinaldirection of the wiring (first direction) D1. Therefore, portions of thebody 91c of the lower layer wiring 91 in which the through openings areformed can be easily transformed by stretching due to the thermalstresses being generated in the lower layer wiring 91, whereby thethermal stresses in the lower layer wiring 91 are satisfactorilyreduced. Consequently, breaking of the upper layer wirings 2a and 2b,connection portions of the upper layer wirings and the lower layerwiring 91 and the like due to the thermal stresses in the lower layerwiring 91 can be suppressed, leading to improved reliability of thesemiconductor device.

In addition, the shape of each through opening of the lower layer wiringis not always a rectangular shape having the first direction D1 as itslongitudinal direction as shown in FIG. 9(a).

For example, FIG. 9(b) illustrates a wiring structure according to amodification example of the ninth embodiment of the invention. In thiswiring structure, through openings of a lower layer wiring haverectangular shapes having a second direction D2 perpendicular to thefirst direction D1 as its longitudinal direction.

More specifically, in FIG. 9(b), reference numeral 95 designates awiring structure of a semiconductor device according to a modificationexample of the ninth embodiment. The same reference numerals as thoseshown in FIG. 9(a) designate the same parts as those in the ninthembodiment.

This wiring structure 95 has a lower layer wiring (first wiring) 96 thatextends along a first direction D1 and has a wiring width direction in asecond direction perpendicular to the first direction D1, where tensilestresses (thermal stresses) are generated inside, and upper layerwirings (second wirings) 2a and 2b that are electrically connected tothe lower layer wiring 96 and are affected by the thermal stresses ofthe lower layer wiring 96. An end portion 2a₁ of the upper layer wiring2a is located on an end portion 96a of the lower layer wiring 96, andconnected to the end portion 96a of the lower layer wiring 96 through acontact hole 7a that is formed in an interlayer insulating film. An endportion 2b₁ of the upper layer wiring 2b is located on the other endportion 96b of the lower layer wiring 96, and connected to the other endportion 96b of the lower layer wiring 96 through a contact hole 7b thatis formed in the interlayer insulating film.

In this case, the lower layer wiring 96 is formed by patterning aplatinum layer that is formed on a silicon substrate 5 via an insulatingfilm. A body 96c, except the end portions 96a and 96b connected to theupper layer wirings 2a and 2b, has a plurality of through openings 96c₁˜96c₄ at predetermined intervals along the first direction D1. Thesethrough openings 96c₁ ˜96c₄ have rectangular shapes, and itslongitudinal direction matches with the second direction D2perpendicular to the first direction D1.

In the modification example of the ninth embodiment with such aconstruction, the lower layer wiring 96 in which the thermal stressesare generated has the plurality of through openings 96c₁ ˜96c₄ ofrectangular shapes that are disposed along its wiring direction, and thelongitudinal direction of the through openings 96c₁ ˜96c₄ of rectangularshapes matches with the second direction D2 perpendicular to the wiringdirection of the lower layer wiring 96 (first direction) D1. Therefore,at portions of the body 96c of the lower layer wiring 96 in which thethrough openings are formed, substantial wiring widths are smaller thanthose in the ninth embodiment, whereby the portions can be more easilytransformed by stretching due to the thermal stresses being generated inthe lower layer wiring 96. Thereby, the thermal stresses in the lowerlayer wiring 96 are reduced more effectively. Consequently, breaking ofthe upper layer wirings 2a and 2b, connection portions of the upperlayer wirings and the lower layer wiring 96 and the like due to thethermal stresses in the lower layer wiring 96 can be further suppressed,leading to further improved reliability of the semiconductor device.

In addition, in the ninth embodiment of the invention, as a multilayerwiring structure of the semiconductor device, the wiring structure 90shown in FIG. 9(a) and the wiring structure 95 as a modification exampleof the structure 90 (refer to FIG. 9(b)) are described. However, thesemiconductor devices according to the ninth embodiment and itsmodification example may have required one of the wiring structures 10,20, 30, 40, 50, 55, 60, 70, 75, 80, 85 and 87 described for the first toeighth embodiments, and the conventional wiring structure 250 shown inFIG. 12, in addition to the wiring structures 90 and 95. Further, asanother modification example of the ninth embodiment, there isconsidered a structure that realizes both of the wiring structures 90and 95.

In any of the first to ninth embodiments of the invention, although thelower layer wiring comprises platinum, the composing material of thelower layer wiring is not always platinum but may be a metallic materialof a high melting point, such as iridium, titanium, and tungsten.

Further, in any of the first to ninth embodiments of the invention,there is described the wiring structure in which thermal stresses aregenerated in the lower layer wiring, and the upper layer wirings areaffected by the thermal stresses. However, this may be a wiringstructure in which thermal stresses are generated in upper layerwirings, and a lower layer wiring is affected by the thermal stresses.

Furthermore, in any of the first to ninth embodiments of the invention,although there is described the case where tensile stresses aregenerated in the lower layer wiring, this lower layer wiring may be onein which expansion stresses are generated.

Furthermore, in any of the first to ninth embodiments of the invention,there is described the lower layer wiring merely comprising a metallicmaterial. However, in a semiconductor device in which a lower layerwiring and a lower electrode (cell plate electrode) constituting, forexample, ferroelectric capacitors of a ferroelectric memory device, areformed by patterning the identical metallic layer, the lower layerwiring may have a structure in which a ferroelectric layer is formed onits surface as shown in FIG. 13(c).

Furthermore, in any of the first to ninth embodiments of the invention,although the wiring structure having the upper layer wirings and thelower layer wiring is described, the structure of the lower layer wiringin the wiring structure according to any of the third to ninthembodiments can be employed for a lower electrode and upper electrodesconstituting ferroelectric capacitors of a ferroelectric memory device.

For example, the structure of the lower layer wiring of any of theseventh and eighth embodiments is effective when the lower layer wiringis used as a lower electrode of ferroelectric capacitors, and aferroelectric layer and upper electrodes of the ferroelectric capacitorsare disposed on regions of the lower layer wiring, except the narrowwiring width portions, thereby constituting the plurality offerroelectric capacitors on the lower layer wiring. In addition,concerning the structure of the lower layer wiring of the ninthembodiment, the lower layer wiring is used as a lower electrode offerroelectric capacitors, and a ferroelectric layer and upper electrodesof the ferroelectric capacitors are disposed on regions of the lowerlayer wiring, except the portions in which the through openings areformed, thereby constituting the plurality of ferroelectric capacitorson the lower layer wiring.

The upper layer wirings in the wiring structure of any of the first andsecond embodiments can be employed as upper layer wirings that areconnected to both ends of a lower electrode constituting ferroelectriccapacitors of a ferroelectric memory device.

Embodiment 10

In a tenth embodiment of the present invention, a description is givenof a device in which the structure of the lower layer wiring accordingto any of the fifth and sixth embodiments is used for lower electrodesconstituting ferroelectric capacitors of a ferroelectric memory device,and the structure of the upper layer wirings according to the firstembodiment is used as upper layer wirings for connecting division partsof the lower electrodes of the ferroelectric memory device.

FIG. 10 is a plan view for explaining a ferroelectric memory deviceaccording to a tenth embodiment of the present invention, whichillustrates a memory cell array in the ferroelectric memory device. FIG.11(a) is a cross-sectional view of a part along a line XIa--XIa shown inFIG. 10, FIG. 11(b) is a cross-sectional view of a part along a lineXIb--XIb shown in FIG. 10, and FIG. 11(c) is a cross-sectional view of apart along a line XIc--XIc shown in FIG. 10. FIG. 12 is a timing chartfor explaining an operation of this ferroelectric memory device.

In the figures, reference numeral 100 designates a memory cell arrayconstituting a ferroelectric memory device. On a silicon substrate 101,transistor regions (in FIG. 10, only transistor regions 120a₁, 120b₁,120b₂ and 120c₁ are shown) are arranged in the form of a matrix along afirst direction D1 and a second direction D2 perpendicular to the firstdirection, and an insulating film 102 for element isolation is formed ona surface region of the silicon substrate 101, except the respectivetransistor regions.

Lower electrodes (first electrodes) (in FIG. 10, only lower electrodes111a and 111b are shown) are disposed as cell plate electrodes,adjacently to the transistor regions of respective lines along the firstdirection D1. The lower electrodes 111a and 111b are formed bypatterning a metallic film comprising a metallic material of a highmelting point, such as platinum, iridium, tungsten and titanium, anddisposed on the insulating film 102 for element isolation via interlayerinsulating films 103. Further, the lower electrodes extend along thefirst direction D1, and have stripe-shaped plans having the seconddirection perpendicular to the first direction as a wiring widthdirection. On surfaces of the lower electrodes, ferroelectric layers 113are formed.

On the ferroelectric layers 113 on the surfaces of the respective lowerelectrodes, upper electrodes (second electrodes) (in FIG. 10, only upperelectrodes 112a₁, 112a₂, 112a₃, 112b₁, 112b₂ and 112b₃ are shown) thatare formed by patterning a metallic film comprising a metallic materialof a high melting point, such as platinum, iridium, tungsten andtitanium, are formed. That is, on the ferroelectric layers 113 on therespective lower electrodes, the plurality of upper electrodes arearranged along the first direction D1. A plan shape of each upperelectrode is a rectangular shape having the first direction D1 as alongitudinal direction. In addition, the area of each upper electrode issmaller than that of the lower electrode. The surfaces of theferroelectric layers 113 and the surfaces of the upper electrodes arecovered with second interlayer insulating films 104.

Here, the lower electrode 111a, the upper electrodes 112a₁, 112a₂ and112a₃ that are located above the lower electrode, and the ferroelectriclayer 113 located between the lower electrode and the upper electrodesconstitute ferroelectric capacitors 110a₁, 110a₂ and 110a ₃. The lowerelectrode 111b, the upper electrodes 112b₁, 112b₂ and 112b₃ that arelocated above the lower electrode, and the ferroelectric layer 113between the lower electrode and the upper electrodes constituteferroelectric capacitors 110b₁, 110b₂ and 110b₃. The ferroelectriccapacitor 110a₁ corresponds to the transistor region 120a₁, theferroelectric capacitors 110a₂ and 110b₂ correspond to the transistorregion 120b₁, and the ferroelectric capacitors 110a₃ and 110b₃correspond to the transistor region 120b₂.

In the tenth embodiment of the invention, in order to reduce variationsin the characteristics of the respective ferroelectric capacitors 110,i.e., variations in polarizability of the ferroelectric layers, and makechanges in the characteristic, i.e., changes in polarizability withpassage of time, less, considering tensile stresses (thermal stresses)generated in the lower electrode and the like, the distances between theadjacent upper electrodes and the areas of the upper electrodes on thelower electrode are made suitable.

Between both of the lower electrodes that sandwich the transistorregions opposing to each other, a pair of word lines (in FIG. 10, onlyword lines 123a, 123b, 123c, 123d, 123e and 123f are shown) comprisingpolysilicon is disposed so as to straddle over the plurality oftransistor regions arranged in a line. A source diffusion region 122 anddrain diffusion regions 121 of a transistor constituting a memory cellare formed on both sides of the word lines in each transistor region.Portions of the word lines located above each transistor regionconstitute gates of the transistor, and are located on the surfaceregion of the substrate 101 via gate insulating films 102a. The surfacesof the diffusion regions 121 and 122 and the word lines are covered withthe first and second interlayer insulating films 103 and 104.

The source diffusion region 122 located between the pair of word linesat each transistor region is connected to a bit line (in FIG. 10, onlybit lines 113b₁, 113b₂ and 113b₃ are shown) extending along the seconddirection perpendicular to the first direction D1, through a contacthole 105b formed in the first and second interlayer insulating films 103and 104. The drain diffusion regions 121 located outside the pair ofword lines at each transistor region are electrically connected to theupper electrodes of the ferroelectric capacitors corresponding to eachtransistor region by connecting wirings 113a. That is, one end of theconnecting wiring 113a is connected to the upper electrode through acontact hole 104a formed in the second interlayer insulating film 104.The other end of the connecting wiring 113a is connected to the draindiffusion region 121 through a contact hole 105a formed in the first andsecond interlayer insulating films 103 and 104.

In this case, the first interlayer insulating film 103 comprises aninsulating material, such as NSG (oxide silicon based) and BPSG (boron,phosphine doped oxide silicon), and the second interlayer insulatingfilm 104 comprises an insulating material, for example, PSG (phosphinedoped oxide silicon).

As a ferroelectric material of the ferroelectric layer 113 of theferroelectric capacitors, KNO₃, PbLa₂ O₃ --ZrO₂ TiO₂, PCTiO₃ --PbZrO₃ orthe like has been known. In addition, PCT International Publication WO93/12542 discloses a ferroelectric material that has extremely lowfatigueness as compared with PbTiO₃ --PbZrO₃, being suitable for aferroelectric memory device.

In the memory cell array 100 of the tenth embodiment, the structure ofthe lower layer wiring according to any of the fifth and sixthembodiments is used for the lower electrodes (cell plate electrodes).More specifically, each of the lower electrodes 111a and 111b has astructure that is divided into a plurality of electrode parts (in FIG.10, only wiring parts 111a₁, 111₂, 111b₁ and 111b₂ are shown), and aplan shape of each electrode part is a zigzag shape. Further, theadjacent electrode parts of the lower electrode are electricallyconnected through a connecting wiring 113c of a U-shaped plan that isformed by patterning an aluminum layer formed on the interlayerinsulating film 104. That is, this connecting wiring 113c is connectedto the corresponding electrode parts of the lower electrode, throughcontact holes 104b that are formed in the interlayer insulating film104.

Both end portions of each lower electrode, concretely, both end portions111a₁₁ and 111a₂₂ of the lower electrode 111a shown in FIG. 10 areconnected to upper layer wirings 106a₁ and 106a₂ that are formed bypatterning an aluminum layer, through contact holes 104c that are formedin the interlayer insulating films 104, respectively, and both endportions 111b₁₁ and 111b₂₂ of the lower electrode 111b are connected toupper layer wirings 106b₁ and 106b₂ that are formed by patterning analuminum layer, through contact holes 104c that are formed in theinterlayer insulating films 104, respectively.

Further, the ferroelectric memory device according to the tenthembodiment is constituted so that the device performs a memory operationof a 1T1C construction, i.e., the device stores information of 1 bit inone memory cell comprising one transistor and one capacitor.

The connecting wirings 113a and 113c and the upper layer wirings 106a₁,106a₂, 106b₁ and 106b₂ may be formed by patterning the identicalaluminum layer, and the connecting wirings and the upper layer wiringsmay be formed by patterning different aluminum layers.

A brief description is given of the operation of the ferroelectricmemory device using this memory cell array construction, with referenceto FIG. 12(a).

Initially, the word line 123b is selected at time t1, and the lowerelectrode (cell plate line) 111a of the ferroelectric capacitor isdriven at time t2 to make the voltage level of the lower electrode thelevel corresponding to the logical voltage "H". Thereby, data of thememory cell capacitor (ferroelectric capacitor) 110a₁ is read out ontothe bit line 113b₁. At this time, a reference voltage is read out ontothe bit line 113b₂.

Then, the voltage level of the cell plate line 111a is changed to thelevel corresponding to the logical voltage "L" at time t3. At time t4,the word line 123b is made in the unselected state, thereby completingthe operation of reading out.

Similarly, the word line 123c is selected at time t5, and the cell plateline 111a is driven at time t6 to make its voltage level the levelcorresponding to the logical voltage "H". Thereby, data of the memorycell capacitor 110₂ is read out onto the bit line 113b₂. At this time, areference voltage is read out onto the bit line 113b₁. Then, the voltagelevel of the cell plate line 111a is changed to the level correspondingto the logical voltage "L" at time t7. At time t8, the word line 123c ismade in the unselected state, thereby completing the operation ofreading out. The memory operation of a 1T1C construction is performed asdescribed above.

In the ferroelectric memory device with such a construction, the lowerelectrodes (cell plate lines) 111a and 111b have structures that arerespectively divided into a plurality of electrode parts 111a₁, 111a₂,111b₁ and 111b₂, and a plan shape of each electrode part is a zigzagshape. Therefore, it is possible to disperse the thermal stresses intothe respective electrode parts, and reduce the thermal stressesgenerated in the electrode parts at bent portions of the zigzag planshapes. Consequently, the thermal stresses of the lower electrodes thataffect the ferroelectric layers on the lower electrodes are reduced, andthe thermal stresses generated in the ferroelectric layer itself arereduced, thereby suppressing variations in the characteristics anddeterioration of the characteristics of the ferroelectric capacitors.

In addition, since the thermal stresses of the lower electrodes thataffect the upper layer wirings 106a₁, 106a₂, 106b₁ and 106b₂respectively connected to the both end portions of the lower electrodes111a and 111b are reduced, production of breaking of the upper layerwirings and breaking of the connection portions of the upper layerwirings and the lower electrodes can be suppressed.

As a result, a ferroelectric memory device having good characteristicsand high reliability can be obtained.

Further, in the tenth embodiment, the wiring portions of the lowerelectrodes have a zigzag shape. Therefore, the upper electrodesconstituting the ferroelectric capacitors can be easily arranged in azigzag shape, whereby it is easy to perform such as the process forsecuring electrical separation regions between the adjacent upperelectrodes.

Furthermore, in the tenth embodiment, although there is described thedevice that performs a memory operation of a 1T1C construction, thememory operation is not always of this construction. For example, amemory operation of a 2T2C (two transistors and two capacitors)construction may be performed.

FIG. 12(b) is a diagram for explaining a ferroelectric memory devicewith a 2T2C (two transistors and two capacitors) construction as amodification example of the tenth embodiment, which illustrates a timingchart of a memory operation of a 2T2C (two transistors and twocapacitors) construction.

A brief description is given of this operation using FIGS. 12(b) and 10.At time t1, the word lines 123b and 123c are selected simultaneously,and the cell plate line (lower electrode) 111a of the ferroelectriccapacitor is driven at time t2 to make its voltage level the levelcorresponding to the logical voltage "H". Thereby, data of the memorycell capacitor 110a₁ is read out onto the bit line 113b₁, and data ofthe memory cell capacitor 110a₂ is read out onto the bit line 113b₂. Thecomplementary data read out from the both memory cell capacitors isamplified by sense amplifiers, thereby reading out data of 1 bit.

Thereafter, the voltage level of the cell plate line 111a is changed tothe level corresponding to the logical voltage "L" at time t3. At timet4, the word lines 123b and 123c are made in the unselected state,thereby completing the operation of reading out. Similarly, the aboveoperation is performed at times t5 to t8, thereby reading out data ofthe memory cell as in the case described above.

As described above, in the ferroelectric memory device having the memorycell array in which the influences by the thermal stresses of the lowerelectrodes are reduced, by simultaneously selecting two word lines 123band 123c, the memory operation of a 2T2C construction can be performed.

In the embodiments of the invention, concerning the lower layer wiringsor the lower electrodes each comprising a material having largecontraction stresses, such as platinum, there are describedconstructions for reducing the thermal stresses that affect the wiringsconnected to the lower layer wirings or lower electrodes and theferroelectric layers formed thereon. However, these constructions areapplicable to wirings or electrodes to which not contraction stressesbut expansion stresses are applied.

INDUSTRIAL AVAILABILITY

According to a semiconductor device of claim 1, the semiconductor deviceincludes a first wiring extending along a first direction, wherestresses are generated inside, and second wirings connected to the firstwiring, and end portions of the second wirings connected to the firstwiring are bent parallel to a second direction that forms apredetermined angle with respect to the first direction. Therefore, theend portions of the second wirings can be easily transformed by thethermal stresses in the first direction that are generated in the firstwiring, thereby effectively reducing the thermal stresses. Consequently,breaking of connection portions of the first and second wirings andbreaking of the second wirings due to the thermal stresses beinggenerated in the first wiring can be suppressed, resulting in improvedreliability of the semiconductor device.

According to a semiconductor device of claim 2, in the semiconductordevice of claim 1, the end portions of the second wirings are bentparallel to a second direction perpendicular to the first direction.Therefore, the end portions of the second wirings can be most easilytransformed by the thermal stresses in the first direction, therebyfurther suppressing production of breaking of the wirings and the likedue to the thermal stresses.

According to a semiconductor device of claim 3, the semiconductor deviceincludes a first wiring extending along a first direction, wherestresses are generated inside, and second wirings connected to the firstwiring, and end portions of the second wirings connected to the firstwiring are disposed to extend along the first direction and toward theinside of the first wiring. Therefore, the tensile stresses generated inthe first wiring act as compressive force to the end portions of thesecond wirings, thereby avoiding breaking at the end portions of thesecond wirings. Further, in this case, the second wirings are arrangedso that the second wirings are led to the upper side or lower side ofthe first wiring, and the bodies of the second wirings form apredetermined angle with respect to the end portions. Accordingly, thebodies can be easily transformed by the stresses in the first direction,thereby effectively reducing the stresses. Consequently, breaking ofconnection portions of the first and second wirings and breaking of thesecond wirings due to the stresses being generated in the first wiringcan be suppressed, resulting in improved reliability of thesemiconductor device.

According to a semiconductor device of claim 4, the semiconductor deviceincludes a first wiring where stresses are generated inside, and secondwirings connected to the first wiring, and the first wiring has at leasta bent portion at its portion. Therefore, the stresses generated in thefirst wiring are dispersed into two directions at the bent portion, anddue to presence of the bent portion, the first wiring can be easilytransformed by the stresses. Consequently, production of breaking of thesecond wirings and the like due to the stresses in the first wiring canbe suppressed, resulting in improved reliability of the semiconductordevice.

Further, it is possible to arrange the second wirings connected to thefirst wiring, parallel to the first wiring. Accordingly, in a wiringlayout in which a plurality of wirings are arranged in parallel, thearea of a region on a substrate that is occupied by the wirings can beeffectively reduced.

According to a semiconductor device of claim 5, in the semiconductordevice of claim 4, the first wiring has a zigzag plan shape and is bentat a plurality of positions. Therefore, the reduction by variation ofthe stresses generated in the first wiring is performed furthereffectively, whereby the influences by the stresses of the first wiringon the second wirings can be further reduced.

According to a semiconductor device of claim 6, in the semiconductordevice of claim 5, sides of the bent portions of the first wiring areparallel to directions, except a direction perpendicular to a firstdirection. Therefore, the size of the first wiring having a zigzag planshape in the direction perpendicular to the first direction is reduced,thereby reducing a region on a substrate that is occupied by the firstwiring.

According to a semiconductor device of claim 7, the semiconductor deviceincludes a first wiring where stresses are generated inside, and secondwirings connected to the first wiring, the whole of the first wiring isdivided into a plurality of wiring parts, and the respective wiringparts are electrically connected to form a predetermined current pathextending from one end of the first wiring to the other end. Therefore,the stresses generated in the first wiring are dispersed into therespective wiring parts, thereby reducing the stresses in the firstwiring. Consequently, production of breaking of the second wirings andthe like due to the stresses in the first wiring can be suppressed,resulting in improved reliability of the semiconductor device.

According to a semiconductor device of claim 8, the semiconductor deviceincludes a first wiring extending along a first direction, wherestresses are generated inside, and second wirings connected to the firstwiring, and the first wiring has narrow wiring width portions withnarrower wiring widths than those of the other portions, at itsportions. Therefore, the first wiring can be more easily transformed bythe stresses in the first direction at the narrow wiring width portionsthan at the other portions, thereby effectively reducing the stresses.Consequently, breaking of connection portions of the first and secondwirings and breaking of the second wirings due to the stresses beinggenerated in the first wiring can be suppressed, resulting in improvedreliability of the semiconductor device.

Further, it is possible to arrange the second wirings connected to thefirst wiring, parallel to the first wiring. Accordingly, in a wiringlayout in which a plurality of wirings are arranged in parallel, thearea of a region on a substrate that is occupied by the wirings can beeffectively reduced.

According to a semiconductor device of claim 9, in the semiconductordevice of claim 8, the narrow wiring width portions are formed bychipping a body of the first wiring from both sides at predeterminedpositions in the wiring path. Therefore, the narrow wiring widthportions are positively transformed by the stresses being generated inthe first wiring, thereby suppressing transformation of the portions ofthe first wiring, except the narrow wiring width portions.

According to a semiconductor device of claim 10, in the semiconductordevice of claim 9, sides of the narrow wiring width portions of thefirst wiring are parallel to directions, except a directionperpendicular to the first direction. Therefore, the areas of chippedparts are reduced, thereby securing wide regions between the adjacentnarrow wiring width portions. For example, when element composingmaterials, such as capacitors, are disposed at the regions between theadjacent narrow wiring width portions, large-capacity capacitors can berealized.

According to a semiconductor device of claim 11, in the semiconductordevice of claim 8, a body of the first wiring has at least a firstnarrow wiring width portion that is formed by chipping one side of thebody, and at least a second narrow wiring width portion that is formedby chipping the other side of the body. Therefore, when the narrowwiring width portions are transformed by the stresses being generated inthe first wiring, the narrow wiring width portions curve so that chippedparts warp backward, thereby exceedingly reducing the stresses by thetransformation of the narrow wiring width portions. Consequently,breaking of the second wirings and the like due to the stresses in thefirst wiring can be further suppressed, resulting in further improvedreliability of the semiconductor device.

According to a semiconductor device of claim 12, in the semiconductordevice of claim 11, the wiring widths of the first and second narrowwiring width portions of the first wiring are larger than 1/2 of thoseof the portions of the first wiring body, except the narrow wiring widthportions, and the center line of the first wiring is divided into partsby the chipped parts at the first and second narrow wiring widthportions. Therefore, in the narrow wiring width portions that are formedby chipping, transformation easily occurs by curving due to the stressesof the first wiring. That is, the narrow wiring width portions can beeasily transformed. Consequently, breaking of the second wirings and thelike due to the stresses in the first wiring can be further suppressed,resulting in exceedingly improved reliability of the semiconductordevice.

According to a semiconductor device of claim 13, in the semiconductordevice of claim 12, sides of the narrow wiring width portions of thefirst wiring at the chipped part sides are parallel to directions,except a direction perpendicular to the first direction. Therefore, theareas of chipped parts are reduced, thereby securing wide regionsbetween the adjacent narrow wiring width portions in the first wiring.For example, when element composing materials, such as capacitors, aredisposed at the regions between the adjacent narrow wiring widthportions, large-capacity capacitors can be realized.

According to a semiconductor device of claim 14, the semiconductordevice includes a first wiring extending along a first direction, wherestresses are generated inside, and second wirings connected to the firstwiring, and the first wiring has at least a through opening in itsportion. Therefore, the portion of the first wiring in which the throughopening is formed can be more easily transformed by the stresses in thefirst direction than the other portions, thereby effectively reducingthe stresses. Consequently, breaking of connection portions of the firstand second wirings and breaking of the second wirings due to thestresses being generated in the first wiring can be suppressed,resulting in improved reliability of the semiconductor device.

According to a semiconductor device of claim 15, in the semiconductordevice of claim 14, the plan shape of the through opening is arectangular shape in which the length in the first direction is smallerthan the length in a direction perpendicular to the first direction.Therefore, the portion of the first wiring in which the through openingis formed can be more easily transformed. Consequently, breaking of thesecond wirings and the like due to the stresses in the first wiring canbe further suppressed, resulting in exceedingly improved reliability ofthe semiconductor device.

According to a semiconductor device of claim 16, in the semiconductordevice of any of claims 1 to 15, the first wiring comprises platinum,iridium, or tungsten, and an insulating layer comprising a ferroelectricmaterial is formed on the surface of the first wiring. Therefore, evenwhen the first wiring comprises a metallic material having a largerthermal expansion coefficient, breaking of the second wirings andbreaking of connection portions of the first and second wirings due tothe thermal stresses being generated in the first wiring can besuppressed. Further, when the insulating layer that is formed on thesurface of the first wiring is used as a dielectric layer of aferroelectric capacitor constituting a ferroelectric memory device,variations in characteristics and characteristic deterioration of theferroelectric capacitors due to the stresses in the first wiring, i.e.,variations in polarizability of the ferroelectric layer and a reductionin polarizability accompanying the use, can be suppressed.

According to a semiconductor device of claim 17, a first electrode offerroelectric capacitors constituting a ferroelectric memory device hasat least a bent portion at its portion. Therefore, stresses generated inthe first electrode are dispersed into two directions at the bentportion, and the first electrode can be easily transformed by thestresses, due to presence of the bent portion. Consequently, stresses ina ferroelectric layer that is formed closely to the first electrode arereduced, thereby suppressing variations in characteristics andcharacteristic deterioration of the ferroelectric capacitors. Further,the influences by the thermal stresses of the first electrode on wiringsthat are connected to the first electrode constituted as a cell plateline are reduced, thereby suppressing production of breaking of thewirings and the like, resulting in improved reliability of theferroelectric memory device.

According to a semiconductor device of claim 18, the whole of a firstelectrode of ferroelectric capacitors constituting a ferroelectricmemory device is divided into a plurality of electrode parts, and therespective electrode parts are electrically connected to form apredetermined current path extending from one end of the first electrodeto the other end. Therefore, stresses, such as thermal stresses, whichare generated in the first electrode are dispersed into the respectiveelectrode parts, thereby reducing the stresses in the first electrode.Consequently, as in claim 17, variations in characteristics andcharacteristic deterioration of the ferroelectric capacitors can besuppressed, and production of breaking of wirings that are connected tothe first electrode and the like can be suppressed, resulting inimproved reliability of the ferroelectric memory device.

According to a semiconductor device of claim 19, in the semiconductordevice of claim 17, the first electrode has a zigzag plan shape and isbent at a plurality of positions. Therefore, the reduction by variationof the stresses generated in the first electrode is performed furthereffectively, whereby the influences by the stresses of the firstelectrode on the wirings connected to the first electrode can be furtherreduced.

According to a semiconductor device of claim 20, in the semiconductordevice of claim 19, first and second word line groups corresponding tofirst and second memory cell groups, and first and second bit linegroups corresponding to the first and second memory cell groups areprovided, and a word line of the first word line group and a word lineof the second word line group are simultaneously selected to read outcomplementary data onto bit lines of the first and second bit linegroups. Therefore, reading out of wrong data due to variations incharacteristics and changes in characteristics of ferroelectriccapacitors can be suppressed. As a result, a ferroelectric memorydevice, in which changes in characteristics, such as variations in thecharacteristics and characteristic deterioration, of ferroelectriccapacitors are less and a 2T2C complementary type operation is stable,can be obtained.

We claim:
 1. A semiconductor device including:a first wiring extendingalong a first direction and having a wiring width direction in a seconddirection perpendicular to the first direction, where stresses aregenerated inside; and second wirings which are situated above the firstwiring, connected to the first wiring through a contact hole, andaffected by the stresses of the first wiring; said second wiringsincluding end portions which are connected to the first wiring, said endportions of said second wirings being bent in a direction which isparallel to a direction that forms a predetermined angle with respect tothe first direction and on a plane including the first direction and thesecond direction.
 2. The semiconductor device as defined in claim 1,wherein;the end portions of the second wirings connected to the firstwiring are bent parallel to the second direction perpendicular to thefirst direction.
 3. The semiconductor device as defined in claim 1,wherein the first wiring comprises at least one member selected from thegroup consisting of platinum, iridium, titanium and tungsten.
 4. Thesemiconductor device as defined in claim 1, further comprising aninsulating layer formed on the surface of the first wiring, saidinsulating layer comprising a ferroelectric material.
 5. A semiconductordevice including:a first wiring extending along a first direction andhaving a wiring width direction and a second direction perpendicular tothe first direction, where stresses are generated inside; and secondwirings which are situated above the first wiring, connected to endportions of the first wiring through a contact hole, and affected by thestresses of the first wiring; wherein the second wirings include endportions which are bent with respect to the remainder of the secondwirings, said end portions being on a plane which is parallel to a planedefined by said first wiring and includes the first direction and thesecond direction, wherein tip parts of the end portions of the secondwirings are connected to the first wiring and are disposed to extendalong the first wiring and toward the inside of the first wiring.
 6. Thesemiconductor device as defined in claim 5, wherein the first wiringcomprises at least one member selected from the group consisting ofplatinum, iridium, titanium and tungsten.
 7. The semiconductor device asdefined in claim 5, further comprising an insulating layer formed on thesurface of the first wiring, said insulating layer comprising aferroelectric material.
 8. A semiconductor device including:a firstwiring extending along a first direction and having a wiring width whichis planarly perpendicular to the first direction; and second wiringswhich are situated above the first wiring, connected to the first wiringthrough a contact hole and affected by the stresses of the first wiring;wherein the first wiring has a bent portion formed at a portion of thefirst wiring; and the second wirings having end portions connected tothe first wiring, said end portions being bent parallel to a directionthat forms a predetermined angle with respect to the first direction ona plane including the first direction and the second direction.
 9. Thesemiconductor device as defined in claim 8, wherein;a body of the firstwiring, except end portions that are connected to the second wirings, isbent at a plurality of positions to have a zigzag plan shape.
 10. Thesemiconductor device as defined in claim 9, wherein;the first wiringbody comprises only oblique wiring parts parallel to directions, excepta direction perpendicular to a first direction, or only the obliquewiring parts and wiring parts parallel to the first direction.
 11. Thesemiconductor device as defined in claim 8, wherein the first wiringcomprises at least one member selected from the group consisting ofplatinum, iridium, titanium and tungsten.
 12. The semiconductor deviceas defined in claim 8, further comprising an insulating layer formed onthe surface of the first wiring, said insulating layer comprising aferroelectric material.
 13. A semiconductor device including:a firstwiring extending along a first direction and having a wiring widthdirection in a second direction perpendicular to the first direction,where stresses are generated inside; and second wirings which aresituated above the first wiring, connected to the first wiring through acontact hole, and affected by the stresses of the first wiring whereinthe whole of the first wiring is divided into a plurality of wiringparts; and the respective wiring parts of the first wiring areelectrically connected by the second wirings to form a predeterminedcurrent path extending from one end of the first wiring to the otherend, the respective wiring parts of the first wiring having wiringlengths, each wiring length being not more than twenty times that of acorresponding wiring width.
 14. A ferroelectric memory device having aplurality of ferroelectric capacitors, said device including:a firstwiring, which extends along a first direction and having a wiring widthdirection in a second direction perpendicular to the first direction,where stresses are generated inside; and second wirings, which areelectrically connected to the first wiring and are affected by thestresses of the first wiring, said first wiring and said second wiringsconstituting the ferroelectric capacitors, wherein the first wiring hasnarrow wiring width portions formed by chipping portions of a firstwiring body, with the exception of end portions that are connected tothe second wirings, the wiring width of each of the narrow wiring widthportions being narrower than that of remaining wiring width portionsexcept the end portions, and the length of the narrow wiring widthportions being shorter than that of the remaining wiring width portions.15. The semiconductor device as defined in claim 14, wherein;the narrowwiring width portions are formed by chipping the first wiring body fromthe both sides at predetermined positions in the wiring path.
 16. Thesemiconductor device as defined in claim 15, wherein;sides of the narrowwiring width portions are parallel to directions, except a directionperpendicular to the first direction.
 17. The semiconductor device asdefined in claim 14, wherein;the first wiring body has at least a firstnarrow wiring width portion that is formed by chipping the body from oneside, and at least a second narrow wiring width portion that is formedby chipping the body from the other side.
 18. The semiconductor deviceas defined in claim 17, wherein;the wiring widths of the first andsecond narrow wiring width portions are smaller than 1/2 of those of theportions of the first wiring body, except the narrow wiring widthportions, and the current path along the center line of the first wiringis divided by the chipped parts at the first and second narrow wiringwidth portions.
 19. The semiconductor device as defined in claim 17,wherein;sides of the first and second narrow wiring width portions atthe chipped part sides are parallel to directions, except a directionperpendicular to the first direction.
 20. The semiconductor device asdefined in claim 8, wherein the first wiring comprises at least onemember selected from the group consisting of platinum, iridium, titaniumand tungsten.
 21. The semiconductor device as defined in claim 8,further comprising an insulating layer formed on the surface of thefirst wiring, said insulating layer comprising a ferroelectric material.22. A ferroelectric memory device having ferroelectric capacitorsincluding:a first wiring which extends along a first direction andhaving a wiring width direction in a second direction perpendicular tothe first direction, where stresses are generated inside; and secondwirings which are situated above the first wiring, connected to thefirst wiring through a contact hole, and affected by the stresses of thefirst wiring, said first wiring and said second wirings constitutingferroelectric capacitors, said first wiring having through openings thatare formed in a first wiring body, said body including end portionswhich are connected to the second wirings.
 23. The semiconductor deviceas defined in claim 22, wherein;the plan shapes of the through openingsare made a rectangular shape in which the length in the first directionis smaller than the length in the second direction perpendicular to thefirst direction.
 24. The semiconductor device as defined in claim 14,wherein the first wiring comprises at least one member selected from thegroup consisting of platinum, iridium, titanium and tungsten.
 25. Thesemiconductor device as defined in claim 14, further comprising aninsulating layer formed on the surface of the first wiring, saidinsulating layer comprising a ferroelectric material.
 26. Asemiconductor device constituting a ferroelectric memory device with aplurality of memory cells comprising transistors and ferroelectriccapacitors, wherein:the ferroelectric capacitor comprises a firstelectrode where stresses are generated inside, a second electrodepositioned opposite to this first electrode, and a ferroelectric layerpositioned between the first and second electrodes; the first electrodehaving a bent portion formed at its portion.
 27. The semiconductordevice as defined in claim 26, wherein;a body of the first electrode,except both end portions, is bent at a plurality of positions to have azigzag plan shape.
 28. The semiconductor device as defined in claim 19,including:first and second memory cell groups each comprising aplurality of memory cells; first and second bit line groupscorresponding to the first and second memory cell groups; first andsecond word line groups provided corresponding to the first and secondmemory cell groups, and comprising a plurality of word lines forcontrolling ON and OFF of transistors constituting the memory cells ofthe corresponding memory cell groups; and sense amplifiers connected tothe respective bit lines of the first and second bit line groups, forsensing storage data on the bit lines, wherein: the first electrode ofthe ferroelectric capacitor constituting each memory cell is connectedto a cell plate line for applying a predetermined driving voltage to theelectrode; the second electrode of the ferroelectric capacitorconstituting each memory cell of the first memory cell group isconnected to the corresponding bit line of the first bit line groupthrough the transistor of the first memory cell group; the secondelectrode of the ferroelectric capacitor constituting each memory cellof the second memory cell group is connected to the corresponding bitline of the second bit line group through the transistor of the secondmemory cell group; and the word line of the first word line group andthe word line of the second word line group are simultaneously selectedso that complementary data is read out onto the corresponding bit linesof both of the bit line groups.
 29. A semiconductor device constitutinga ferroelectric memory device with a plurality of memory cellscomprising transistors and ferroelectric capacitors, wherein:theferroelectric capacitor comprises a first electrode that extends along afirst direction, where stresses are generated inside, a second electrodepositioned opposite to this first electrode, and a ferroelectric layerpositioned between the first and second electrodes; the whole of thefirst electrode being divided into a plurality of electrode parts, andthe respective electrode parts being electrically connected to form apredetermined current path extending from one end of the first electrodeto the other end.